lkml.org 
[lkml]   [2020]   [Nov]   [6]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH v2 5/5] arm64: dts: lx2160a: fix FlexSPI clock
Am 2020-11-06 03:00, schrieb Leo Li:
>> -----Original Message-----
>> From: Michael Walle <michael@walle.cc>
>> Sent: Thursday, November 5, 2020 1:35 PM
>> To: linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-
>> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org
>> Cc: Michael Turquette <mturquette@baylibre.com>; Stephen Boyd
>> <sboyd@kernel.org>; Rob Herring <robh+dt@kernel.org>; Shawn Guo
>> <shawnguo@kernel.org>; Leo Li <leoyang.li@nxp.com>; Michael Walle
>> <michael@walle.cc>
>> Subject: [PATCH v2 5/5] arm64: dts: lx2160a: fix FlexSPI clock
>>
>> Now that we have a proper driver for the FlexSPI interface use it.
>> This will fix
>> SCK frequency switching on Layerscape SoCs.
>>
>> This was only compile time tested.
>>
>> Signed-off-by: Michael Walle <michael@walle.cc>
>> ---
>> Changes since v1:
>> - none
>>
>> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 15 +++++++++++++--
>> 1 file changed, 13 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> index 83072da6f6c6..6e375e80bd35 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>> @@ -659,9 +659,20 @@
>> };
>>
>> dcfg: syscon@1e00000 {
>> - compatible = "fsl,lx2160a-dcfg", "syscon";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "fsl,lx2160a-dcfg", "syscon", "simple-
>> mfd";
>> reg = <0x0 0x1e00000 0x0 0x10000>;
>> + ranges = <0x0 0x0 0x1e00000 0x10000>;
>> little-endian;
>> +
>> + fspi_clk: clock-controller@900 {
>> + compatible = "fsl,lx2160a-flexspi-clk";
>> + reg = <0x900 0x4>;
>> + #clock-cells = <0>;
>> + clocks = <&clockgen 4 0>;
>
> This is different from the current <&clockgen 4 3>, is it an intended
> change?

Yes, this change was intended. At least on the LS1028A this clock
divider is
connected to the platform base clock. I don't know why there was
"<&clockgen 4 3>" in the first place. But because the clkgen clock
cannot
be changed it didn't matter before this commit. The flexspi driver only
calls clk_set_rate(), never clk_get_rate(). On the LS1028A I actually
meassured the resulting SCK frequency.
Looking at Figure 7. (Clock subsystem block diagram) in the LX2160A RM,
this
seems to be the case here, too.

-michael

\
 
 \ /
  Last update: 2022-09-17 16:09    [W:0.051 / U:1.056 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site