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    SubjectRE: [PATCH v7 2/7] irqchip/gic-v3: Enable support for SGIs to act as NMIs
    Date
    Hi Sumit,

    > Subject: [PATCH v7 2/7] irqchip/gic-v3: Enable support for SGIs to act as
    > NMIs
    >
    > Add support to handle SGIs as pseudo NMIs. As SGIs or IPIs default to a
    > special flow handler: handle_percpu_devid_fasteoi_ipi(), so skip NMI handler
    > update in case of SGIs.
    >
    > Also, enable NMI support prior to gic_smp_init() as allocation of SGIs as
    > IRQs/NMIs happen as part of this routine.
    >
    > Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
    > ---
    > drivers/irqchip/irq-gic-v3.c | 29 +++++++++++++++++++++--------
    > 1 file changed, 21 insertions(+), 8 deletions(-)
    >
    > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index
    > 16fecc0..7010ae2 100644
    > --- a/drivers/irqchip/irq-gic-v3.c
    > +++ b/drivers/irqchip/irq-gic-v3.c
    > @@ -461,6 +461,7 @@ static u32 gic_get_ppi_index(struct irq_data *d)
    > static int gic_irq_nmi_setup(struct irq_data *d) {
    > struct irq_desc *desc = irq_to_desc(d->irq);
    > + u32 idx;
    >
    > if (!gic_supports_nmi())
    > return -EINVAL;
    > @@ -478,16 +479,22 @@ static int gic_irq_nmi_setup(struct irq_data *d)
    > return -EINVAL;
    >
    > /* desc lock should already be held */
    > - if (gic_irq_in_rdist(d)) {
    > - u32 idx = gic_get_ppi_index(d);
    > + switch (get_intid_range(d)) {
    > + case SGI_RANGE:
    > + break;
    > + case PPI_RANGE:
    > + case EPPI_RANGE:
    > + idx = gic_get_ppi_index(d);
    >
    > /* Setting up PPI as NMI, only switch handler for first NMI */
    > if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
    > refcount_set(&ppi_nmi_refs[idx], 1);
    > desc->handle_irq =
    > handle_percpu_devid_fasteoi_nmi;
    > }
    > - } else {
    > + break;
    > + default:
    > desc->handle_irq = handle_fasteoi_nmi;
    > + break;
    > }
    >
    > gic_irq_set_prio(d, GICD_INT_NMI_PRI); @@ -498,6 +505,7 @@
    > static int gic_irq_nmi_setup(struct irq_data *d) static void
    > gic_irq_nmi_teardown(struct irq_data *d) {
    > struct irq_desc *desc = irq_to_desc(d->irq);
    > + u32 idx;
    >
    > if (WARN_ON(!gic_supports_nmi()))
    > return;
    > @@ -515,14 +523,20 @@ static void gic_irq_nmi_teardown(struct irq_data *d)
    > return;
    >
    > /* desc lock should already be held */
    > - if (gic_irq_in_rdist(d)) {
    > - u32 idx = gic_get_ppi_index(d);
    > + switch (get_intid_range(d)) {
    > + case SGI_RANGE:
    > + break;
    > + case PPI_RANGE:
    > + case EPPI_RANGE:
    > + idx = gic_get_ppi_index(d);
    >
    > /* Tearing down NMI, only switch handler for last NMI */
    > if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
    > desc->handle_irq = handle_percpu_devid_irq;
    > - } else {
    > + break;
    > + default:
    > desc->handle_irq = handle_fasteoi_irq;
    > + break;
    > }
    >
    > gic_irq_set_prio(d, GICD_INT_DEF_PRI); @@ -1708,6 +1722,7 @@
    > static int __init gic_init_bases(void __iomem *dist_base,
    >
    > gic_dist_init();
    > gic_cpu_init();
    > + gic_enable_nmi_support();
    > gic_smp_init();
    > gic_cpu_pm_init();
    >
    > @@ -1719,8 +1734,6 @@ static int __init gic_init_bases(void __iomem
    > *dist_base,
    > gicv2m_init(handle, gic_data.domain);
    > }
    >
    > - gic_enable_nmi_support();
    > -
    > return 0;
    >
    > out_free:
    > --
    > 2.7.4

    I checked for this patch and I think that's good.
    I've tested this patch with FX1000 used my other patches.
    The result is as follows.

    $ echo 1 > /proc/sys/kernel/panic_on_rcu_stal
    $ echo HARDLOCKUP > /sys/kernel/debug/provoke-crash/DIRECT
    : kernel panics and crash kernel boot
    : makedumpfile saves the system state at HARDLOCKUP in vmcore.

    crash utility:
    #7 [fffffe0029e4fd30] lkdtm_HARDLOCKUP at fffffe0010856eec
    #8 [fffffe0029e4fd40] direct_entry at fffffe0010856c94
    #9 [fffffe0029e4fd90] full_proxy_write at fffffe001055ced0
    #10 [fffffe0029e4fdd0] vfs_write at fffffe001047436c
    #11 [fffffe0029e4fe10] ksys_write at fffffe001047466c
    #12 [fffffe0029e4fe60] __arm64_sys_write at fffffe0010474718
    #13 [fffffe0029e4fe70] do_el0_svc at fffffe00101590cc
    #14 [fffffe0029e4fea0] el0_svc at fffffe0010147a30
    #15 [fffffe0029e4feb0] el0_sync_handler at fffffe001014835c
    #16 [fffffe0029e4fff0] el0_sync at fffffe0010142c14

    Best regards,

    Yuichi Ito

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