Messages in this thread | | | Subject | [PATCH 0/5] Fix x2apic enablement and allow up to 32768 CPUs without IR where supported | From | David Woodhouse <> | Date | Wed, 07 Oct 2020 13:20:20 +0100 |
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Splitting out the simpler parts of my previous patch set. The full support for per-irqdomain affinity limits will take a bit more work but this part is quite simple.
Since we don't yet have per-irqdomain affinity, we currently attempt to avoid bringing CPUs online at all if they can't be targeted by external interrupts. Except we still let them get hotplugged later... which is moderately suboptimal.
Fix that, and support the hypervisor enlightenment which at least extends the range of targetable APIC IDs to 15 bits, as seen in the patch at https://patchwork.kernel.org/patch/11816693/ for qemu.
David Woodhouse (5): x86/apic: Fix x2apic enablement without interrupt remapping x86/msi: Only use high bits of MSI address for DMAR unit x86/ioapic: Handle Extended Destination ID field in RTE x86/apic: Support 15 bits of APIC ID in IOAPIC/MSI where available x86/kvm: Add KVM_FEATURE_MSI_EXT_DEST_ID
Documentation/virt/kvm/cpuid.rst | 4 ++++ arch/x86/include/asm/apic.h | 1 + arch/x86/include/asm/io_apic.h | 3 ++- arch/x86/include/asm/mpspec.h | 1 + arch/x86/include/asm/x86_init.h | 2 ++ arch/x86/include/uapi/asm/kvm_para.h | 1 + arch/x86/kernel/apic/apic.c | 27 +++++++++++++++++++++------ arch/x86/kernel/apic/io_apic.c | 19 +++++++++++++------ arch/x86/kernel/apic/msi.c | 41 +++++++++++++++++++++++++++++++++++------ arch/x86/kernel/apic/x2apic_phys.c | 9 +++++++++ arch/x86/kernel/kvm.c | 6 ++++++ arch/x86/kernel/x86_init.c | 1 + 12 files changed, 96 insertions(+), 19 deletions(-) [unhandled content-type:application/x-pkcs7-signature] | |