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SubjectRe: [PATCH 23/25] ASoC: sun8i-codec: Generalize AIF clock control
Hi,

On Wed, Sep 30, 2020 at 09:11:46PM -0500, Samuel Holland wrote:
> The AIF clock control register has the same layout for all three AIFs.
> The only difference between them is that AIF3 is missing some fields. We
> can reuse the same register field definitions for all three registers,
> and use the DAI ID to select the correct register address.
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> sound/soc/sunxi/sun8i-codec.c | 64 +++++++++++++++++++----------------
> 1 file changed, 34 insertions(+), 30 deletions(-)
>
> diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
> index 032a3f714dbb..1c34502ac47a 100644
> --- a/sound/soc/sunxi/sun8i-codec.c
> +++ b/sound/soc/sunxi/sun8i-codec.c
> @@ -37,23 +37,23 @@
> #define SUN8I_MOD_CLK_ENA_DAC 2
> #define SUN8I_MOD_RST_CTL 0x014
> #define SUN8I_MOD_RST_CTL_AIF1 15
> #define SUN8I_MOD_RST_CTL_ADC 3
> #define SUN8I_MOD_RST_CTL_DAC 2
> #define SUN8I_SYS_SR_CTRL 0x018
> #define SUN8I_SYS_SR_CTRL_AIF1_FS 12
> #define SUN8I_SYS_SR_CTRL_AIF2_FS 8
> -#define SUN8I_AIF1CLK_CTRL 0x040
> -#define SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD 15
> -#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV 13
> -#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV 9
> -#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV 6
> -#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4
> -#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2
> +#define SUN8I_AIF_CLK_CTRL(n) (0x040 * (1 + (n)))
> +#define SUN8I_AIF_CLK_CTRL_MSTR_MOD 15
> +#define SUN8I_AIF_CLK_CTRL_CLK_INV 13
> +#define SUN8I_AIF_CLK_CTRL_BCLK_DIV 9
> +#define SUN8I_AIF_CLK_CTRL_LRCK_DIV 6
> +#define SUN8I_AIF_CLK_CTRL_WORD_SIZ 4
> +#define SUN8I_AIF_CLK_CTRL_DATA_FMT 2
> #define SUN8I_AIF1_ADCDAT_CTRL 0x044
> #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15
> #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14
> #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC 10
> #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC 8
> #define SUN8I_AIF1_DACDAT_CTRL 0x048
> #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15
> #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14
> @@ -83,21 +83,21 @@
> #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10
> #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9
> #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8
>
> #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK GENMASK(9, 8)
> #define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK GENMASK(5, 4)
> #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12)
> #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8)
> -#define SUN8I_AIF1CLK_CTRL_AIF1_CLK_INV_MASK GENMASK(14, 13)
> -#define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9)
> -#define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6)
> -#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_MASK GENMASK(5, 4)
> -#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT_MASK GENMASK(3, 2)
> +#define SUN8I_AIF_CLK_CTRL_CLK_INV_MASK GENMASK(14, 13)
> +#define SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK GENMASK(12, 9)
> +#define SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK GENMASK(8, 6)
> +#define SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK GENMASK(5, 4)
> +#define SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK GENMASK(3, 2)
>
> #define SUN8I_CODEC_PASSTHROUGH_SAMPLE_RATE 48000
>
> #define SUN8I_CODEC_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 |\
> SNDRV_PCM_FMTBIT_S16_LE |\
> SNDRV_PCM_FMTBIT_S20_LE |\
> SNDRV_PCM_FMTBIT_S24_LE |\
> SNDRV_PCM_FMTBIT_S20_3LE|\
> @@ -223,32 +223,34 @@ static int sun8i_codec_update_sample_rate(struct sun8i_codec *scodec)
> hw_rate << SUN8I_SYS_SR_CTRL_AIF1_FS);
>
> return 0;
> }
>
> static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
> {
> struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai);
> + u32 reg = SUN8I_AIF_CLK_CTRL(dai->id);
> u32 format, invert, value;
>
> /* clock masters */
> switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
> case SND_SOC_DAIFMT_CBS_CFS: /* Codec slave, DAI master */
> value = 0x1;
> break;
> case SND_SOC_DAIFMT_CBM_CFM: /* Codec Master, DAI slave */
> value = 0x0;
> break;
> default:
> return -EINVAL;
> }
> - regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
> - BIT(SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD),
> - value << SUN8I_AIF1CLK_CTRL_AIF1_MSTR_MOD);
> +
> + regmap_update_bits(scodec->regmap, reg,
> + BIT(SUN8I_AIF_CLK_CTRL_MSTR_MOD),
> + value << SUN8I_AIF_CLK_CTRL_MSTR_MOD);

I guess it would be more readable without the intermediate variable to
store the register.

With that fixed,
Acked-by: Maxime Ripard <mripard@kernel.org>

Maxime
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