Messages in this thread | | | From | David Laight <> | Subject | RE: [PATCH] mtd: spi-nor: Fix 3-or-4 address byte mode logic | Date | Sun, 4 Oct 2020 21:36:20 +0000 |
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From: Bert Vermeulen > Sent: 04 October 2020 22:12 > > On 10/2/20 9:50 AM, David Laight wrote: > > From: Bert Vermeulen > >> The SoCs I'm dealing with have an SPI_ADDR_SEL pin, indicating whether it > >> should be in 3 or 4-byte mode. The vendor's hacked-up U-Boot sets the mode > >> accordingly, as does their BSP. It seems to me like a misfeature, and I want > >> to just ignore it and do reasonable JEDEC things, but I have the problem > >> that the flash chip can be in 4-byte mode by the time it gets to my spi-nor > >> driver. > > > > If these are the devices I think they are, can't you read the > > non-volatile config word (bit 0) to find out whether the device > > expects a 3 or 4 byte address and how many 'idle' clocks there > > are before the read data? > > I'm working with Realtek RTL838x/RTL839x SoCs. Reading it out is a > pretty convoluted procedure involving different I/O registers depending > on the SoC model.
How do they manage to let you do read/write without 'read control'. Actually I can imagine...
The problem we had was getting the IO pins to link up to user logic on an Altera Cyclone-V fpga. Then it was just a 'SMOP' to get reads and write converted to nibble 'bit-bang' with the chipselect and output enable (IIRC) controlled by the register address. I doubt any 'standard' interface is as efficient.
I think I found a hardware bug in the chips we are using. There seemed to be a timing window in which the 'read status' command (after a write/erase) was completely ignored by the device. Everything looked write on a scope - but the data line wasn't driven.
David
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