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SubjectRe: [PATCH] drm/msm/dsi: save PLL registers across first PHY reset
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Hello,

On 07/10/2020 03:10, benl-kernelpatches@squareup.com wrote:
> From: Benjamin Li <benl@squareup.com>
>
> Take advantage of previously-added support for persisting PLL
> registers across DSI PHY disable/enable cycles (see 328e1a6
> 'drm/msm/dsi: Save/Restore PLL status across PHY reset') to
> support persisting across the very first DSI PHY enable at
> boot.

Interesting enough, this breaks exactly on 8016. On DB410c with latest
bootloader and w/o splash screen this patch causes boot freeze. Without
this patch the board would successfully boot with display routed to HDMI.

> The bootloader may have left the PLL registers in a non-default
> state. For example, for dsi_pll_28nm.c on 8x16/8x39, the byte
> clock mux's power-on reset configuration is to bypass DIV1, but
> depending on bandwidth requirements[1] the bootloader may have
> set the DIV1 path.
>
> When the byte clock mux is registered with the generic clock
> framework at probe time, the framework reads & caches the value
> of the mux bit field (the initial clock parent). After PHY enable,
> when clk_set_rate is called on the byte clock, the framework
> assumes there is no need to reparent, and doesn't re-write the
> mux bit field. But PHY enable resets PLL registers, so the mux
> bit field actually silently reverted to the DIV1 bypass path.
> This causes the byte clock to be off by a factor of e.g. 2 for
> our tested WXGA panel.
>
> The above issue manifests as the display not working and a
> constant stream of FIFO/LP0 contention errors.
>
> [1] The specific requirement for triggering the DIV1 path (and
> thus this issue) on 28nm is a panel with pixel clock <116.7MHz
> (one-third the minimum VCO setting). FHD/1080p (~145MHz) is fine,
> WXGA/1280x800 (~75MHz) is not.
>
> Signed-off-by: Benjamin Li <benl@squareup.com>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 009f5b843dd1..139b4a5aaf86 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -621,6 +621,22 @@ static int dsi_phy_driver_probe(struct platform_device *pdev)
> phy->pll = NULL;
> }
>
> + /*
> + * As explained in msm_dsi_phy_enable, resetting the DSI PHY (as done
> + * in dsi_mgr_phy_enable) silently changes its PLL registers to power-on
> + * defaults, but the generic clock framework manages and caches several
> + * of the PLL registers. It initializes these caches at registration
> + * time via register read.
> + *
> + * As a result, we need to save DSI PLL registers once at probe in order
> + * for the first call to msm_dsi_phy_enable to successfully bring PLL
> + * registers back in line with what the generic clock framework expects.
> + *
> + * Subsequent PLL restores during msm_dsi_phy_enable will always be
> + * paired with PLL saves in msm_dsi_phy_disable.
> + */
> + msm_dsi_pll_save_state(phy->pll);
> +
> dsi_phy_disable_resource(phy);
>
> platform_set_drvdata(pdev, phy);
>


--
With best wishes
Dmitry

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