Messages in this thread | | | Date | Sat, 3 Oct 2020 16:40:51 +0800 | From | kernel test robot <> | Subject | arch/arm/include/asm/arch_gicv3.h:44:2: error: implicit declaration of function 'write_sysreg' |
| |
Hi Peng,
FYI, the error/warning still remains.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: d3d45f8220d60a0b2aaaacf8fb2be4e6ffd9008e commit: d82bcef5157de1368c08244a846ab968b3e5cb7e soc: imx: select ARM_GIC_V3 for i.MX8M date: 3 months ago config: arm-randconfig-r002-20201003 (attached as .config) compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0 reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=d82bcef5157de1368c08244a846ab968b3e5cb7e git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git git fetch --no-tags linus master git checkout d82bcef5157de1368c08244a846ab968b3e5cb7e # save the attached .config to linux build tree COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>):
In file included from include/linux/irqchip/arm-gic-v3.h:662, from drivers/irqchip/irq-gic-v3.c:24: arch/arm/include/asm/arch_gicv3.h: In function 'write_ICC_PMR_EL1': >> arch/arm/include/asm/arch_gicv3.h:44:2: error: implicit declaration of function 'write_sysreg' [-Werror=implicit-function-declaration] 44 | write_sysreg(val, a32); \ | ^~~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:51:1: note: in expansion of macro 'CPUIF_MAP' 51 | CPUIF_MAP(ICC_PMR, ICC_PMR_EL1) | ^~~~~~~~~ >> arch/arm/include/asm/arch_gicv3.h:22:20: error: implicit declaration of function '__ACCESS_CP15' [-Werror=implicit-function-declaration] 22 | #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0) | ^~~~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro 'CPUIF_MAP' 44 | write_sysreg(val, a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:51:11: note: in expansion of macro 'ICC_PMR' 51 | CPUIF_MAP(ICC_PMR, ICC_PMR_EL1) | ^~~~~~~ >> arch/arm/include/asm/arch_gicv3.h:22:34: error: 'c4' undeclared (first use in this function) 22 | #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0) | ^~ arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro 'CPUIF_MAP' 44 | write_sysreg(val, a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:51:11: note: in expansion of macro 'ICC_PMR' 51 | CPUIF_MAP(ICC_PMR, ICC_PMR_EL1) | ^~~~~~~ arch/arm/include/asm/arch_gicv3.h:22:34: note: each undeclared identifier is reported only once for each function it appears in 22 | #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0) | ^~ arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro 'CPUIF_MAP' 44 | write_sysreg(val, a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:51:11: note: in expansion of macro 'ICC_PMR' 51 | CPUIF_MAP(ICC_PMR, ICC_PMR_EL1) | ^~~~~~~ >> arch/arm/include/asm/arch_gicv3.h:22:41: error: 'c6' undeclared (first use in this function) 22 | #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0) | ^~ arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro 'CPUIF_MAP' 44 | write_sysreg(val, a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:51:11: note: in expansion of macro 'ICC_PMR' 51 | CPUIF_MAP(ICC_PMR, ICC_PMR_EL1) | ^~~~~~~ arch/arm/include/asm/arch_gicv3.h: In function 'read_ICC_PMR_EL1': >> arch/arm/include/asm/arch_gicv3.h:48:9: error: implicit declaration of function 'read_sysreg' [-Werror=implicit-function-declaration] 48 | return read_sysreg(a32); \ | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:51:1: note: in expansion of macro 'CPUIF_MAP' 51 | CPUIF_MAP(ICC_PMR, ICC_PMR_EL1) | ^~~~~~~~~ >> arch/arm/include/asm/arch_gicv3.h:22:34: error: 'c4' undeclared (first use in this function) 22 | #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0) | ^~ arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro 'CPUIF_MAP' 48 | return read_sysreg(a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:51:11: note: in expansion of macro 'ICC_PMR' 51 | CPUIF_MAP(ICC_PMR, ICC_PMR_EL1) | ^~~~~~~ >> arch/arm/include/asm/arch_gicv3.h:22:41: error: 'c6' undeclared (first use in this function) 22 | #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0) | ^~ arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro 'CPUIF_MAP' 48 | return read_sysreg(a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:51:11: note: in expansion of macro 'ICC_PMR' 51 | CPUIF_MAP(ICC_PMR, ICC_PMR_EL1) | ^~~~~~~ arch/arm/include/asm/arch_gicv3.h: In function 'write_ICC_AP0R0_EL1': >> arch/arm/include/asm/arch_gicv3.h:29:40: error: 'c12' undeclared (first use in this function) 29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) | ^~~ arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro 'CPUIF_MAP' 44 | write_sysreg(val, a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:30:21: note: in expansion of macro '__ICC_AP0Rx' 30 | #define ICC_AP0R0 __ICC_AP0Rx(0) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:52:11: note: in expansion of macro 'ICC_AP0R0' 52 | CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1) | ^~~~~~~~~ >> arch/arm/include/asm/arch_gicv3.h:29:48: error: 'c8' undeclared (first use in this function); did you mean 'u8'? 29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) | ^~ arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro 'CPUIF_MAP' 44 | write_sysreg(val, a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:30:21: note: in expansion of macro '__ICC_AP0Rx' 30 | #define ICC_AP0R0 __ICC_AP0Rx(0) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:52:11: note: in expansion of macro 'ICC_AP0R0' 52 | CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1) | ^~~~~~~~~ arch/arm/include/asm/arch_gicv3.h: In function 'read_ICC_AP0R0_EL1': >> arch/arm/include/asm/arch_gicv3.h:29:40: error: 'c12' undeclared (first use in this function) 29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) | ^~~ arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro 'CPUIF_MAP' 48 | return read_sysreg(a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:30:21: note: in expansion of macro '__ICC_AP0Rx' 30 | #define ICC_AP0R0 __ICC_AP0Rx(0) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:52:11: note: in expansion of macro 'ICC_AP0R0' 52 | CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1) | ^~~~~~~~~ >> arch/arm/include/asm/arch_gicv3.h:29:48: error: 'c8' undeclared (first use in this function); did you mean 'u8'? 29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) | ^~ arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro 'CPUIF_MAP' 48 | return read_sysreg(a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:30:21: note: in expansion of macro '__ICC_AP0Rx' 30 | #define ICC_AP0R0 __ICC_AP0Rx(0) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:52:11: note: in expansion of macro 'ICC_AP0R0' 52 | CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1) | ^~~~~~~~~ arch/arm/include/asm/arch_gicv3.h: In function 'write_ICC_AP0R1_EL1': >> arch/arm/include/asm/arch_gicv3.h:29:40: error: 'c12' undeclared (first use in this function) 29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) | ^~~ arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro 'CPUIF_MAP' 44 | write_sysreg(val, a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:31:21: note: in expansion of macro '__ICC_AP0Rx' 31 | #define ICC_AP0R1 __ICC_AP0Rx(1) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:53:11: note: in expansion of macro 'ICC_AP0R1' 53 | CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1) | ^~~~~~~~~ >> arch/arm/include/asm/arch_gicv3.h:29:48: error: 'c8' undeclared (first use in this function); did you mean 'u8'? 29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) | ^~ arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro 'CPUIF_MAP' 44 | write_sysreg(val, a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:31:21: note: in expansion of macro '__ICC_AP0Rx' 31 | #define ICC_AP0R1 __ICC_AP0Rx(1) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:53:11: note: in expansion of macro 'ICC_AP0R1' 53 | CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1) | ^~~~~~~~~ arch/arm/include/asm/arch_gicv3.h: In function 'read_ICC_AP0R1_EL1': >> arch/arm/include/asm/arch_gicv3.h:29:40: error: 'c12' undeclared (first use in this function) 29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) | ^~~ arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro 'CPUIF_MAP' 48 | return read_sysreg(a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:31:21: note: in expansion of macro '__ICC_AP0Rx' 31 | #define ICC_AP0R1 __ICC_AP0Rx(1) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:53:11: note: in expansion of macro 'ICC_AP0R1' 53 | CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1) | ^~~~~~~~~ >> arch/arm/include/asm/arch_gicv3.h:29:48: error: 'c8' undeclared (first use in this function); did you mean 'u8'? 29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) | ^~ arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro 'CPUIF_MAP' 48 | return read_sysreg(a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:31:21: note: in expansion of macro '__ICC_AP0Rx' 31 | #define ICC_AP0R1 __ICC_AP0Rx(1) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:53:11: note: in expansion of macro 'ICC_AP0R1' 53 | CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1) | ^~~~~~~~~ arch/arm/include/asm/arch_gicv3.h: In function 'write_ICC_AP0R2_EL1': >> arch/arm/include/asm/arch_gicv3.h:29:40: error: 'c12' undeclared (first use in this function) 29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) | ^~~ arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro 'CPUIF_MAP' 44 | write_sysreg(val, a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:32:21: note: in expansion of macro '__ICC_AP0Rx' 32 | #define ICC_AP0R2 __ICC_AP0Rx(2) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:54:11: note: in expansion of macro 'ICC_AP0R2' 54 | CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1) | ^~~~~~~~~ >> arch/arm/include/asm/arch_gicv3.h:29:48: error: 'c8' undeclared (first use in this function); did you mean 'u8'? 29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) | ^~ arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro 'CPUIF_MAP' 44 | write_sysreg(val, a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:32:21: note: in expansion of macro '__ICC_AP0Rx' 32 | #define ICC_AP0R2 __ICC_AP0Rx(2) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:54:11: note: in expansion of macro 'ICC_AP0R2' 54 | CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1) | ^~~~~~~~~ arch/arm/include/asm/arch_gicv3.h: In function 'read_ICC_AP0R2_EL1': >> arch/arm/include/asm/arch_gicv3.h:29:40: error: 'c12' undeclared (first use in this function) 29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) | ^~~ arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro 'CPUIF_MAP' 48 | return read_sysreg(a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:32:21: note: in expansion of macro '__ICC_AP0Rx' 32 | #define ICC_AP0R2 __ICC_AP0Rx(2) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:54:11: note: in expansion of macro 'ICC_AP0R2' 54 | CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1) | ^~~~~~~~~ >> arch/arm/include/asm/arch_gicv3.h:29:48: error: 'c8' undeclared (first use in this function); did you mean 'u8'? 29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) | ^~ arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro 'CPUIF_MAP' 48 | return read_sysreg(a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:32:21: note: in expansion of macro '__ICC_AP0Rx' 32 | #define ICC_AP0R2 __ICC_AP0Rx(2) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:54:11: note: in expansion of macro 'ICC_AP0R2' 54 | CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1) | ^~~~~~~~~ arch/arm/include/asm/arch_gicv3.h: In function 'write_ICC_AP0R3_EL1': >> arch/arm/include/asm/arch_gicv3.h:29:40: error: 'c12' undeclared (first use in this function) 29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) | ^~~ arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro 'CPUIF_MAP' 44 | write_sysreg(val, a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:33:21: note: in expansion of macro '__ICC_AP0Rx' 33 | #define ICC_AP0R3 __ICC_AP0Rx(3) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:55:11: note: in expansion of macro 'ICC_AP0R3' 55 | CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1) | ^~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:29:48: error: 'c8' undeclared (first use in this function); did you mean 'u8'? 29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) | ^~ arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro 'CPUIF_MAP' 44 | write_sysreg(val, a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:33:21: note: in expansion of macro '__ICC_AP0Rx' 33 | #define ICC_AP0R3 __ICC_AP0Rx(3) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:55:11: note: in expansion of macro 'ICC_AP0R3' 55 | CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1) | ^~~~~~~~~ arch/arm/include/asm/arch_gicv3.h: In function 'read_ICC_AP0R3_EL1': arch/arm/include/asm/arch_gicv3.h:29:40: error: 'c12' undeclared (first use in this function) 29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) | ^~~ arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro 'CPUIF_MAP' 48 | return read_sysreg(a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:33:21: note: in expansion of macro '__ICC_AP0Rx' 33 | #define ICC_AP0R3 __ICC_AP0Rx(3) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:55:11: note: in expansion of macro 'ICC_AP0R3' 55 | CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1) | ^~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:29:48: error: 'c8' undeclared (first use in this function); did you mean 'u8'? 29 | #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) | ^~ arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro 'CPUIF_MAP' 48 | return read_sysreg(a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:33:21: note: in expansion of macro '__ICC_AP0Rx' 33 | #define ICC_AP0R3 __ICC_AP0Rx(3) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:55:11: note: in expansion of macro 'ICC_AP0R3' 55 | CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1) | ^~~~~~~~~ arch/arm/include/asm/arch_gicv3.h: In function 'write_ICC_AP1R0_EL1': arch/arm/include/asm/arch_gicv3.h:35:40: error: 'c12' undeclared (first use in this function) 35 | #define __ICC_AP1Rx(x) __ACCESS_CP15(c12, 0, c9, x) | ^~~ arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro 'CPUIF_MAP' 44 | write_sysreg(val, a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:36:21: note: in expansion of macro '__ICC_AP1Rx' 36 | #define ICC_AP1R0 __ICC_AP1Rx(0) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:56:11: note: in expansion of macro 'ICC_AP1R0' 56 | CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1) | ^~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:35:48: error: 'c9' undeclared (first use in this function) 35 | #define __ICC_AP1Rx(x) __ACCESS_CP15(c12, 0, c9, x) | ^~ arch/arm/include/asm/arch_gicv3.h:44:20: note: in definition of macro 'CPUIF_MAP' 44 | write_sysreg(val, a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:36:21: note: in expansion of macro '__ICC_AP1Rx' 36 | #define ICC_AP1R0 __ICC_AP1Rx(0) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:56:11: note: in expansion of macro 'ICC_AP1R0' 56 | CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1) | ^~~~~~~~~ arch/arm/include/asm/arch_gicv3.h: In function 'read_ICC_AP1R0_EL1': arch/arm/include/asm/arch_gicv3.h:35:40: error: 'c12' undeclared (first use in this function) 35 | #define __ICC_AP1Rx(x) __ACCESS_CP15(c12, 0, c9, x) | ^~~ arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro 'CPUIF_MAP' 48 | return read_sysreg(a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:36:21: note: in expansion of macro '__ICC_AP1Rx' 36 | #define ICC_AP1R0 __ICC_AP1Rx(0) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:56:11: note: in expansion of macro 'ICC_AP1R0' 56 | CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1) | ^~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:35:48: error: 'c9' undeclared (first use in this function) 35 | #define __ICC_AP1Rx(x) __ACCESS_CP15(c12, 0, c9, x) | ^~ arch/arm/include/asm/arch_gicv3.h:48:21: note: in definition of macro 'CPUIF_MAP' 48 | return read_sysreg(a32); \ | ^~~ arch/arm/include/asm/arch_gicv3.h:36:21: note: in expansion of macro '__ICC_AP1Rx' 36 | #define ICC_AP1R0 __ICC_AP1Rx(0) | ^~~~~~~~~~~ arch/arm/include/asm/arch_gicv3.h:56:11: note: in expansion of macro 'ICC_AP1R0' 56 | CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1) | ^~~~~~~~~ arch/arm/include/asm/arch_gicv3.h: In function 'write_ICC_AP1R1_EL1': arch/arm/include/asm/arch_gicv3.h:35:40: error: 'c12' undeclared (first use in this function) ..
vim +/write_sysreg +44 arch/arm/include/asm/arch_gicv3.h
d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 17 d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 18 #define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1) d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 @19 #define ICC_DIR __ACCESS_CP15(c12, 0, c11, 1) d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 20 #define ICC_IAR1 __ACCESS_CP15(c12, 0, c12, 0) d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 @21 #define ICC_SGI1R __ACCESS_CP15_64(0, c12) d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 @22 #define ICC_PMR __ACCESS_CP15(c4, 0, c6, 0) d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 23 #define ICC_CTLR __ACCESS_CP15(c12, 0, c12, 4) d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 24 #define ICC_SRE __ACCESS_CP15(c12, 0, c12, 5) d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 25 #define ICC_IGRPEN1 __ACCESS_CP15(c12, 0, c12, 7) 91ef84428a86b75 Daniel Thompson 2016-08-19 26 #define ICC_BPR1 __ACCESS_CP15(c12, 0, c12, 3) e99da7c6f51b487 Julien Thierry 2019-01-31 27 #define ICC_RPR __ACCESS_CP15(c12, 0, c11, 3) d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 28 d6062a6d62c643a Marc Zyngier 2018-03-09 @29 #define __ICC_AP0Rx(x) __ACCESS_CP15(c12, 0, c8, 4 | x) d6062a6d62c643a Marc Zyngier 2018-03-09 30 #define ICC_AP0R0 __ICC_AP0Rx(0) d6062a6d62c643a Marc Zyngier 2018-03-09 31 #define ICC_AP0R1 __ICC_AP0Rx(1) d6062a6d62c643a Marc Zyngier 2018-03-09 32 #define ICC_AP0R2 __ICC_AP0Rx(2) d6062a6d62c643a Marc Zyngier 2018-03-09 33 #define ICC_AP0R3 __ICC_AP0Rx(3) d6062a6d62c643a Marc Zyngier 2018-03-09 34 d6062a6d62c643a Marc Zyngier 2018-03-09 @35 #define __ICC_AP1Rx(x) __ACCESS_CP15(c12, 0, c9, x) d6062a6d62c643a Marc Zyngier 2018-03-09 36 #define ICC_AP1R0 __ICC_AP1Rx(0) d6062a6d62c643a Marc Zyngier 2018-03-09 37 #define ICC_AP1R1 __ICC_AP1Rx(1) d6062a6d62c643a Marc Zyngier 2018-03-09 38 #define ICC_AP1R2 __ICC_AP1Rx(2) d6062a6d62c643a Marc Zyngier 2018-03-09 39 #define ICC_AP1R3 __ICC_AP1Rx(3) d6062a6d62c643a Marc Zyngier 2018-03-09 40 a078bedf17c2e43 Vladimir Murzin 2016-09-12 41 #define CPUIF_MAP(a32, a64) \ a078bedf17c2e43 Vladimir Murzin 2016-09-12 42 static inline void write_ ## a64(u32 val) \ a078bedf17c2e43 Vladimir Murzin 2016-09-12 43 { \ a078bedf17c2e43 Vladimir Murzin 2016-09-12 @44 write_sysreg(val, a32); \ a078bedf17c2e43 Vladimir Murzin 2016-09-12 45 } \ a078bedf17c2e43 Vladimir Murzin 2016-09-12 46 static inline u32 read_ ## a64(void) \ a078bedf17c2e43 Vladimir Murzin 2016-09-12 47 { \ a078bedf17c2e43 Vladimir Murzin 2016-09-12 @48 return read_sysreg(a32); \ a078bedf17c2e43 Vladimir Murzin 2016-09-12 49 } \ a078bedf17c2e43 Vladimir Murzin 2016-09-12 50 33625282adaaba9 Marc Zyngier 2018-03-20 51 CPUIF_MAP(ICC_PMR, ICC_PMR_EL1) d6062a6d62c643a Marc Zyngier 2018-03-09 52 CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1) d6062a6d62c643a Marc Zyngier 2018-03-09 53 CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1) d6062a6d62c643a Marc Zyngier 2018-03-09 54 CPUIF_MAP(ICC_AP0R2, ICC_AP0R2_EL1) d6062a6d62c643a Marc Zyngier 2018-03-09 55 CPUIF_MAP(ICC_AP0R3, ICC_AP0R3_EL1) d6062a6d62c643a Marc Zyngier 2018-03-09 56 CPUIF_MAP(ICC_AP1R0, ICC_AP1R0_EL1) d6062a6d62c643a Marc Zyngier 2018-03-09 57 CPUIF_MAP(ICC_AP1R1, ICC_AP1R1_EL1) d6062a6d62c643a Marc Zyngier 2018-03-09 58 CPUIF_MAP(ICC_AP1R2, ICC_AP1R2_EL1) d6062a6d62c643a Marc Zyngier 2018-03-09 59 CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1) d6062a6d62c643a Marc Zyngier 2018-03-09 60 a078bedf17c2e43 Vladimir Murzin 2016-09-12 61 #define read_gicreg(r) read_##r() a078bedf17c2e43 Vladimir Murzin 2016-09-12 62 #define write_gicreg(v, r) write_##r(v) a078bedf17c2e43 Vladimir Murzin 2016-09-12 63 d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 64 /* Low-level accessors */ d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 65 d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 66 static inline void gic_write_eoir(u32 irq) d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 67 { 4f2546384150e78 Vladimir Murzin 2016-09-12 68 write_sysreg(irq, ICC_EOIR1); d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 69 isb(); d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 70 } d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 71 d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 72 static inline void gic_write_dir(u32 val) d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 73 { 4f2546384150e78 Vladimir Murzin 2016-09-12 74 write_sysreg(val, ICC_DIR); d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 75 isb(); d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 76 } d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 77 d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 78 static inline u32 gic_read_iar(void) d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 79 { 4f2546384150e78 Vladimir Murzin 2016-09-12 80 u32 irqstat = read_sysreg(ICC_IAR1); d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 81 8f318526a292c5e Marc Zyngier 2016-02-18 82 dsb(sy); 4f2546384150e78 Vladimir Murzin 2016-09-12 83 d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 84 return irqstat; d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 85 } d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 86 d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 87 static inline void gic_write_ctlr(u32 val) d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 88 { 4f2546384150e78 Vladimir Murzin 2016-09-12 89 write_sysreg(val, ICC_CTLR); d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 90 isb(); d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 91 } d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 92 eda0d04acc5e317 Shanker Donthineni 2017-10-06 93 static inline u32 gic_read_ctlr(void) eda0d04acc5e317 Shanker Donthineni 2017-10-06 94 { eda0d04acc5e317 Shanker Donthineni 2017-10-06 95 return read_sysreg(ICC_CTLR); eda0d04acc5e317 Shanker Donthineni 2017-10-06 96 } eda0d04acc5e317 Shanker Donthineni 2017-10-06 97 d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 98 static inline void gic_write_grpen1(u32 val) d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 99 { 4f2546384150e78 Vladimir Murzin 2016-09-12 100 write_sysreg(val, ICC_IGRPEN1); d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 101 isb(); d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 102 } d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 103 d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 104 static inline void gic_write_sgi1r(u64 val) d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 105 { 4f2546384150e78 Vladimir Murzin 2016-09-12 106 write_sysreg(val, ICC_SGI1R); d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 107 } d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 108 d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 109 static inline u32 gic_read_sre(void) d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 110 { 4f2546384150e78 Vladimir Murzin 2016-09-12 111 return read_sysreg(ICC_SRE); d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 112 } d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 113 d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 114 static inline void gic_write_sre(u32 val) d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 115 { 4f2546384150e78 Vladimir Murzin 2016-09-12 116 write_sysreg(val, ICC_SRE); d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 117 isb(); d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 118 } d5cd50d318f70fc Jean-Philippe Brucker 2015-10-01 119 91ef84428a86b75 Daniel Thompson 2016-08-19 120 static inline void gic_write_bpr1(u32 val) 91ef84428a86b75 Daniel Thompson 2016-08-19 121 { 3d9cd95f90b2987 Marc Zyngier 2016-09-23 122 write_sysreg(val, ICC_BPR1); 91ef84428a86b75 Daniel Thompson 2016-08-19 123 } 91ef84428a86b75 Daniel Thompson 2016-08-19 124 e99da7c6f51b487 Julien Thierry 2019-01-31 125 static inline u32 gic_read_pmr(void) e99da7c6f51b487 Julien Thierry 2019-01-31 126 { e99da7c6f51b487 Julien Thierry 2019-01-31 127 return read_sysreg(ICC_PMR); e99da7c6f51b487 Julien Thierry 2019-01-31 128 } e99da7c6f51b487 Julien Thierry 2019-01-31 129 e99da7c6f51b487 Julien Thierry 2019-01-31 130 static inline void gic_write_pmr(u32 val) e99da7c6f51b487 Julien Thierry 2019-01-31 131 { e99da7c6f51b487 Julien Thierry 2019-01-31 132 write_sysreg(val, ICC_PMR); e99da7c6f51b487 Julien Thierry 2019-01-31 133 } e99da7c6f51b487 Julien Thierry 2019-01-31 134 e99da7c6f51b487 Julien Thierry 2019-01-31 135 static inline u32 gic_read_rpr(void) e99da7c6f51b487 Julien Thierry 2019-01-31 136 { e99da7c6f51b487 Julien Thierry 2019-01-31 137 return read_sysreg(ICC_RPR); e99da7c6f51b487 Julien Thierry 2019-01-31 @138 } e99da7c6f51b487 Julien Thierry 2019-01-31 139
:::::: The code at line 44 was first introduced by commit :::::: a078bedf17c2e43819fea54bdfd5793845142e3a ARM: gic-v3: Introduce 32-to-64-bit mappings for GICv3 cpu registers
:::::: TO: Vladimir Murzin <vladimir.murzin@arm.com> :::::: CC: Christoffer Dall <christoffer.dall@linaro.org>
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