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    Subject[PATCH 04/12] clk: mediatek: Clean up the pll_en_bit from en_mask on MT6779
    Date
    remove pll_en_bit(bit0) from en_mask to make en_mask a pure en_mask
    that only used for pll dividers.

    Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
    ---
    drivers/clk/mediatek/clk-mt6779.c | 24 ++++++++++++------------
    1 file changed, 12 insertions(+), 12 deletions(-)

    diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
    index 9766ccc..d8444ed 100644
    --- a/drivers/clk/mediatek/clk-mt6779.c
    +++ b/drivers/clk/mediatek/clk-mt6779.c
    @@ -1178,33 +1178,33 @@
    _pcw_chg_reg, NULL)

    static const struct mtk_pll_data plls[] = {
    - PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, BIT(0),
    + PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
    PLL_AO, 0, 22, 8, 0x0204, 24, 0, 0, 0, 0x0204, 0, 0),
    - PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, BIT(0),
    + PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, 0,
    PLL_AO, 0, 22, 8, 0x0214, 24, 0, 0, 0, 0x0214, 0, 0),
    - PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, BIT(0),
    + PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, 0,
    PLL_AO, 0, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0, 0),
    - PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, BIT(0),
    + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0,
    (HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0,
    0x0234, 0, 0),
    - PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, BIT(0),
    + PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, 0,
    (HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24,
    0, 0, 0, 0x0244, 0, 0),
    - PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, BIT(0),
    + PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, 0,
    0, 0, 22, 8, 0x0254, 24, 0, 0, 0, 0x0254, 0, 0),
    - PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, BIT(0),
    + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, 0,
    0, 0, 22, 8, 0x0264, 24, 0, 0, 0, 0x0264, 0, 0),
    - PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, BIT(0),
    + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0,
    0, 0, 22, 8, 0x0274, 24, 0, 0, 0, 0x0274, 0, 0),
    - PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, BIT(0),
    + PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, 0,
    (HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24,
    0, 0, 0, 0x02b4, 0, 0),
    - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, BIT(0),
    + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, 0,
    (HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24,
    0, 0, 0, 0x0284, 0, 0),
    - PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, BIT(0),
    + PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, 0,
    0, 0, 32, 8, 0x02C0, 1, 0, 0x14, 0, 0x02C4, 0, 0x2C0),
    - PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, BIT(0),
    + PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, 0,
    0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4),
    };

    --
    1.8.1.1.dirty
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