Messages in this thread Patch in this message | | | From | Weiyi Lu <> | Subject | [PATCH v4 25/34] clk: mediatek: Add MT8192 ipesys clock support | Date | Thu, 22 Oct 2020 20:37:18 +0800 |
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Add MT8192 ipesys clock provider
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> --- drivers/clk/mediatek/Kconfig | 6 ++++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8192-ipe.c | 64 +++++++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8192-ipe.c
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 037f74f2..df75a09 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -527,6 +527,12 @@ config COMMON_CLK_MT8192_IMP_IIC_WRAP_WS help This driver supports MediaTek MT8192 imp_iic_wrap_ws clocks. +config COMMON_CLK_MT8192_IPESYS + bool "Clock driver for MediaTek MT8192 ipesys" + depends on COMMON_CLK_MT8192 + help + This driver supports MediaTek MT8192 ipesys clocks. + config COMMON_CLK_MT8516 bool "Clock driver for MediaTek MT8516" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 4faa9ad..5fe21f9 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -75,5 +75,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_N) += clk-mt8192-imp_iic_wrap_n.o obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_S) += clk-mt8192-imp_iic_wrap_s.o obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_W) += clk-mt8192-imp_iic_wrap_w.o obj-$(CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP_WS) += clk-mt8192-imp_iic_wrap_ws.o +obj-$(CONFIG_COMMON_CLK_MT8192_IPESYS) += clk-mt8192-ipe.o obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o diff --git a/drivers/clk/mediatek/clk-mt8192-ipe.c b/drivers/clk/mediatek/clk-mt8192-ipe.c new file mode 100644 index 0000000..304dca4 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8192-ipe.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (c) 2020 MediaTek Inc. +// Author: Weiyi Lu <weiyi.lu@mediatek.com> + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include <dt-bindings/clock/mt8192-clk.h> + +static const struct mtk_gate_regs ipe_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_IPE(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate ipe_clks[] = { + GATE_IPE(CLK_IPE_LARB19, "ipe_larb19", "ipe_sel", 0), + GATE_IPE(CLK_IPE_LARB20, "ipe_larb20", "ipe_sel", 1), + GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2), + GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3), + GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4), + GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5), + GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 6), + GATE_IPE(CLK_IPE_GALS, "ipe_gals", "ipe_sel", 8), +}; + +static int clk_mt8192_ipe_probe(struct platform_device *pdev) +{ + struct clk_onecell_data *clk_data; + struct device_node *node = pdev->dev.of_node; + int r; + + clk_data = mtk_alloc_clk_data(CLK_IPE_NR_CLK); + if (!clk_data) + return -ENOMEM; + + r = mtk_clk_register_gates(node, ipe_clks, ARRAY_SIZE(ipe_clks), clk_data); + if (r) + return r; + + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); +} + +static const struct of_device_id of_match_clk_mt8192_ipe[] = { + { .compatible = "mediatek,mt8192-ipesys", }, + {} +}; + +static struct platform_driver clk_mt8192_ipe_drv = { + .probe = clk_mt8192_ipe_probe, + .driver = { + .name = "clk-mt8192-ipe", + .of_match_table = of_match_clk_mt8192_ipe, + }, +}; + +builtin_platform_driver(clk_mt8192_ipe_drv); -- 1.8.1.1.dirty | |