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    SubjectRe: [PATCH] PCI: dwc: Added link up check in map_bus of dw_child_pcie_ops
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    Hi Lorenzo,

    On 19/10/20 9:43 pm, Lorenzo Pieralisi wrote:
    > On Mon, Oct 12, 2020 at 04:41:11AM +0000, Z.q. Hou wrote:
    >
    > [...]
    >
    >>>>> Yeah, I don't see any registers in the DRA7x PCIe wrapper for
    >>>>> disabling error forwarding.
    >>>>
    >>>> It's a DWC port logic register AFAICT, but perhaps not present in all
    >>> versions.
    >>>
    >>> Okay. I see there's a register PCIECTRL_PL_AXIS_SLV_ERR_RESP which has a
    >>> reset value of 0.
    >>>
    >>> It has four bit-fields, RESET_TIMEOUT_ERR_MAP, NO_VID_ERR_MAP,
    >>> DBI_ERR_MAP and SLAVE_ERR_MAP. I'm not seeing any difference in
    >>> behavior if I set all these bits. Maybe it requires platform support too. I'll
    >>> check this with our design team.
    >>
    >> In DWC v4.40a databook, there is a bit AMBA_ERROR_RESPONSE_GLOBAL
    >> which controls if enable the error forwarding. The *MAP bits only
    >> determine which error (SLVERR or DECERR) will be forwarded to AXI/AHB
    >> bus.
    >
    > I have not seen a follow-up to this but I would like to, still keen
    > on avoiding this patch if possible - if this is port logic it should
    > be common across controllers implementations I assume.
    >
    > Gustavo, Kishon ?

    Atleast in the TI DRA7 TRM, I could see only
    PCIECTRL_PL_AXIS_SLV_ERR_RESP and PCIECTRL_PL_AXIS_SLV_TIMEOUT register
    but no global error response bit. I'd have expected configuring
    SLV_ERR_RESP would have disabled error forwarding, but I don't see any
    change in behavior if I modify the value of PCIECTRL_PL_AXIS_SLV_ERR_RESP.

    TI PCIe controller in DRA7 is not directly connected to AXI/AHB but
    there is an intermediary bridge. So I suspect there is some issue on how
    the controller is integrated in TI platform. Since the board hangs, I
    couldn't get lot of visibility of controller state.

    Thanks
    Kishon

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