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SubjectRe: [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU
On Wed, Sep 30, 2020 at 03:06:29PM +0800, Yong Wu wrote:
> This patch adds decriptions for mt8192 IOMMU and SMI.
>
> mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
> table format. The M4U-SMI HW diagram is as below:
>
> EMI
> |
> M4U
> |
> ------------
> SMI Common
> ------------
> |
> +-------+------+------+----------------------+-------+
> | | | | ...... | |
> | | | | | |
> larb0 larb1 larb2 larb4 ...... larb19 larb20
> disp0 disp1 mdp vdec IPE IPE
>
> All the connections are HW fixed, SW can NOT adjust it.
>
> mt8192 M4U support 0~16GB iova range. we preassign different engines
> into different iova ranges:
>
> domain-id module iova-range larbs
> 0 disp 0 ~ 4G larb0/1
> 1 vcodec 4G ~ 8G larb4/5/7
> 2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20
> 3 CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10
> 4 CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5
>
> The iova range for CCU0/1(camera control unit) is HW requirement.
>
> Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> .../bindings/iommu/mediatek,iommu.yaml | 9 +-
> .../mediatek,smi-common.yaml | 5 +-
> .../memory-controllers/mediatek,smi-larb.yaml | 3 +-
> include/dt-bindings/memory/mt8192-larb-port.h | 239 ++++++++++++++++++
> 4 files changed, 251 insertions(+), 5 deletions(-)
> create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h

I see it depends on previous patches but does it have to be within one
commit? Is it not bisectable? The memory changes/bindings could go via
memory tree if this is split.

Best regards,
Krzysztof

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