Messages in this thread | | | From | Arvind Sankar <> | Date | Mon, 19 Oct 2020 17:22:47 -0400 | Subject | Re: [PATCH 3/5] x86/boot/compressed/64: Check SEV encryption in 64-bit boot-path |
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On Mon, Oct 19, 2020 at 10:33:45PM +0200, Joerg Roedel wrote: > Hi Arvind, > > On Mon, Oct 19, 2020 at 01:00:08PM -0400, Arvind Sankar wrote: > > On Mon, Oct 19, 2020 at 05:11:19PM +0200, Joerg Roedel wrote: > > > + > > > + /* Store value to memory and keep it in %r10 */ > > > + movq %r10, sev_check_data(%rip) > > > + > > > > Does there need to be a cache flush/invalidation between this and the > > read below to avoid just reading back from cache, or will the hardware > > take care of that? > > No, a cache flush is not needed. When the C bit position is correct, > then the data will be mapped encrypted with the old and the new > page-table. If the C bit position is wrong, the access goes to a > different physical address.
Ok.
> > > > + /* Backup current %cr3 value to restore it later */ > > > + movq %cr3, %r11 > > > + > > > + /* Switch to new %cr3 - This might unmap the stack */ > > > + movq %rdi, %cr3 > > > > Does there need to be a TLB flush after this? When executed from the > > main kernel's head code, CR4.PGE is enabled, and if the original page > > mapping had the global bit set (the decompressor stub sets that in the > > identity mapping), won't the read below still use the original encrypted > > mapping if we don't explicitly flush it? > > The check only really matters for the boot CPU, not for the secondary > CPUs. IIRC at this point in boot CR4.PGE is still off. > > Regards, > > Joerg >
The boot cpu also enables CR4.PGE -- that code is shared between boot and secondary cpus. The boot cpu jumps to the first "1" label below, just before the call to sev_verify_cbit you're adding.
/* Form the CR3 value being sure to include the CR3 modifier */ addq $(init_top_pgt - __START_KERNEL_map), %rax 1:
/* Enable PAE mode, PGE and LA57 */ movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx #ifdef CONFIG_X86_5LEVEL testl $1, __pgtable_l5_enabled(%rip) jz 1f orl $X86_CR4_LA57, %ecx 1: #endif movq %rcx, %cr4
/* Setup early boot stage 4-/5-level pagetables. */ addq phys_base(%rip), %rax movq %rax, %cr3
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