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    SubjectRe: [PATCH v1 0/8] perf c2c: Sort cacheline with LLC load
    On Thu, Oct 15, 2020 at 12:05:06PM -0300, Arnaldo Carvalho de Melo wrote:
    > Em Thu, Oct 15, 2020 at 03:50:33PM +0100, Leo Yan escreveu:
    > > If the memory event doesn't contain HITM tag (like Arm SPE), it cannot
    > > rely on HITM display to report cache false sharing. Alternatively, we
    > > can use the LLC access and multi-threads info to locate the potential
    > > false sharing's data address, and if we connect with source code and
    > > analyze the multi-threads' execution timing, if can conclude load and
    > > store the same cache line at the meantime, thus this can be helpful for
    > > resolve the cache false sharing issue.
    > >
    > > This patch set is to enable the display with sorting on LLC load
    > > accesses; it adds dimensions for total LLC hit and LLC load accesses,
    > > and these dimensions are used for shared cache line table and pareto.
    > >
    > > This patch set is dependend on the patch set "perf c2c: Refine the
    > > organization of metrics" [1].
    > >
    > > [1] https://lore.kernel.org/patchwork/cover/1321499/
    >
    > Ok, that one is applied and will appear publicly as soon as it goes thru
    > my usual set of build tests.

    Thank you, Arnaldo!

    Leo

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