Messages in this thread | | | Subject | Re: [PATCH v10 8/8] arm: dts: rockchip: Add NFC node for RK3036 SoC | From | Kever Yang <> | Date | Wed, 14 Oct 2020 08:28:09 +0800 |
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On 2020/9/30 上午10:09, Yifeng Zhao wrote: > Add NAND FLASH Controller(NFC) node for RK3036 SoC. > > Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> > --- > > Changes in v10: None > Changes in v9: None > Changes in v8: None > Changes in v7: None > Changes in v6: None > Changes in v5: None > Changes in v4: None > Changes in v3: None > Changes in v2: None > > arch/arm/boot/dts/rk3036.dtsi | 52 +++++++++++++++++++++++++++++++++++ > 1 file changed, 52 insertions(+)
Looks good to me,
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
Thanks, - Kever
> > diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi > index 093567022386..dda5a1f79aca 100644 > --- a/arch/arm/boot/dts/rk3036.dtsi > +++ b/arch/arm/boot/dts/rk3036.dtsi > @@ -292,6 +292,21 @@ > status = "disabled"; > }; > > + nfc: nand-controller@10500000 { > + compatible = "rockchip,rk3036-nfc", > + "rockchip,rk2928-nfc"; > + reg = <0x10500000 0x4000>; > + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; > + clock-names = "ahb", "nfc"; > + assigned-clocks = <&cru SCLK_NANDC>; > + assigned-clock-rates = <150000000>; > + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 > + &flash_rdn &flash_rdy &flash_wrn>; > + pinctrl-names = "default"; > + status = "disabled"; > + }; > + > cru: clock-controller@20000000 { > compatible = "rockchip,rk3036-cru"; > reg = <0x20000000 0x1000>; > @@ -643,6 +658,43 @@ > }; > }; > > + nfc { > + flash_ale: flash-ale { > + rockchip,pins = <2 RK_PA0 1 &pcfg_pull_default>; > + }; > + > + flash_bus8: flash-bus8 { > + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_default>, > + <1 RK_PD1 1 &pcfg_pull_default>, > + <1 RK_PD2 1 &pcfg_pull_default>, > + <1 RK_PD3 1 &pcfg_pull_default>, > + <1 RK_PD4 1 &pcfg_pull_default>, > + <1 RK_PD5 1 &pcfg_pull_default>, > + <1 RK_PD6 1 &pcfg_pull_default>, > + <1 RK_PD7 1 &pcfg_pull_default>; > + }; > + > + flash_cle: flash-cle { > + rockchip,pins = <2 RK_PA1 1 &pcfg_pull_default>; > + }; > + > + flash_csn0: flash-csn0 { > + rockchip,pins = <2 RK_PA6 1 &pcfg_pull_default>; > + }; > + > + flash_rdn: flash-rdn { > + rockchip,pins = <2 RK_PA3 1 &pcfg_pull_default>; > + }; > + > + flash_rdy: flash-rdy { > + rockchip,pins = <2 RK_PA4 1 &pcfg_pull_default>; > + }; > + > + flash_wrn: flash-wrn { > + rockchip,pins = <2 RK_PA2 1 &pcfg_pull_default>; > + }; > + }; > + > emac { > emac_xfer: emac-xfer { > rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
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