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    SubjectRe: [PATCH v6 08/17] ARM: dts: add SD5203 dts
    On Wed, Sep 30, 2020 at 11:17:03AM +0800, Zhen Lei wrote:
    > From: Kefeng Wang <wangkefeng.wang@huawei.com>
    >
    > Add sd5203.dts for Hisilicon SD5203 SoC platform.
    >
    > Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
    > Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
    > ---
    > arch/arm/boot/dts/Makefile | 2 +
    > arch/arm/boot/dts/sd5203.dts | 96 ++++++++++++++++++++++++++++++++++++++++++++
    > 2 files changed, 98 insertions(+)
    > create mode 100644 arch/arm/boot/dts/sd5203.dts
    >
    > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
    > index 4572db3fa5ae302..1d1262df5c55907 100644
    > --- a/arch/arm/boot/dts/Makefile
    > +++ b/arch/arm/boot/dts/Makefile
    > @@ -357,6 +357,8 @@ dtb-$(CONFIG_ARCH_MPS2) += \
    > mps2-an399.dtb
    > dtb-$(CONFIG_ARCH_MOXART) += \
    > moxart-uc7112lx.dtb
    > +dtb-$(CONFIG_ARCH_SD5203) += \
    > + sd5203.dtb
    > dtb-$(CONFIG_SOC_IMX1) += \
    > imx1-ads.dtb \
    > imx1-apf9328.dtb
    > diff --git a/arch/arm/boot/dts/sd5203.dts b/arch/arm/boot/dts/sd5203.dts
    > new file mode 100644
    > index 000000000000000..3cc9a23910be62e
    > --- /dev/null
    > +++ b/arch/arm/boot/dts/sd5203.dts
    > @@ -0,0 +1,96 @@
    > +// SPDX-License-Identifier: GPL-2.0-only
    > +/*
    > + * Copyright (c) 2020 Hisilicon Limited.
    > + *
    > + * DTS file for Hisilicon SD5203 Board
    > + */
    > +
    > +/dts-v1/;
    > +
    > +/ {
    > + model = "Hisilicon SD5203";
    > + compatible = "H836ASDJ", "hisilicon,sd5203";
    > + interrupt-parent = <&vic>;
    > + #address-cells = <1>;
    > + #size-cells = <1>;
    > +
    > + chosen {
    > + bootargs="console=ttyS0,9600 earlycon=uart8250,mmio32,0x1600d000";
    > + };
    > +
    > + aliases {
    > + serial0 = &uart0;
    > + };
    > +
    > + cpus {
    > + #address-cells = <1>;
    > + #size-cells = <0>;
    > +
    > + cpu0 {
    > + device_type = "cpu";
    > + compatible = "arm,arm926ej-s";
    > + reg = <0x0>;
    > + };
    > + };
    > +
    > + memory@30000000 {
    > + device_type = "memory";
    > + reg = <0x30000000 0x8000000>;
    > + };
    > +
    > + soc {
    > + #address-cells = <1>;
    > + #size-cells = <1>;
    > + compatible = "simple-bus";
    > + ranges;
    > +
    > + vic: interrupt-controller@10130000 {
    > + compatible = "snps,dw-apb-ictl";
    > + reg = <0x10130000 0x1000>;
    > + interrupt-controller;
    > + #interrupt-cells = <1>;
    > + };
    > +
    > + refclk125mhz: refclk125mhz {
    > + compatible = "fixed-clock";
    > + #clock-cells = <0>;
    > + clock-frequency = <125000000>;

    Is this a reference clock really in the SoC? Not outside, e.g. property
    of the board?

    Best regards,
    Krzysztof

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