lkml.org 
[lkml]   [2020]   [Oct]   [1]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: [PATCH 2/2] arm64: dts: imx8mm-kontron: Add support for ultra high speed modes on SD card
From
Date
On 01.10.20 14:34, Schrempf Frieder wrote:
> From: Frieder Schrempf <frieder.schrempf@kontron.de>
>
> In order to use ultra high speed modes (UHS) on the SD card slot, we
> add matching pinctrls and fix the voltage switching for LDO5 of the
> PMIC, by providing the SD_VSEL pin as GPIO to the PMIC driver.
>
> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
> ---
> .../dts/freescale/imx8mm-kontron-n801x-s.dts | 27 +++++++++++++++++++
> .../freescale/imx8mm-kontron-n801x-som.dtsi | 2 ++
> 2 files changed, 29 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
> index 389e735b2880..6913aefa56aa 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
> @@ -190,8 +190,11 @@
> };
>
> &usdhc2 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> pinctrl-names = "default";

And before anyone complains: The above line needs to be dropped of course.

> pinctrl-0 = <&pinctrl_usdhc2>;
> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
> vmmc-supply = <&reg_vdd_3v3>;
> vqmmc-supply = <&reg_nvcc_sd>;
> cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
> @@ -320,4 +323,28 @@
> MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
> >;
> };
> +
> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
> + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
> + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
> + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
> + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
> + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
> + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
> + >;
> + };
> +
> + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> + fsl,pins = <
> + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
> + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
> + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
> + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
> + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
> + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
> + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
> + >;
> + };
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
> index 5c6a660f4395..282a56fb3949 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
> @@ -85,6 +85,7 @@
> pinctrl-0 = <&pinctrl_pmic>;
> interrupt-parent = <&gpio1>;
> interrupts = <0 GPIO_ACTIVE_LOW>;
> + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
>
> regulators {
> reg_vdd_soc: BUCK1 {
> @@ -224,6 +225,7 @@
> pinctrl_pmic: pmicgrp {
> fsl,pins = <
> MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x41
> + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x41
> >;
> };
>
>

\
 
 \ /
  Last update: 2020-10-01 15:15    [W:0.094 / U:0.184 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site