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Subject[RFC PATCH v1 05/10] ARM: dts: rockchip: add nandc nodes for rk3288
Date
From: Jianqun Xu <jay.xu@rock-chips.com>

Add nandc nodes for rk3288.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm/boot/dts/rk3288.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 415c75f57..704a101d8 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -30,6 +30,8 @@
mshc1 = &sdmmc;
mshc2 = &sdio0;
mshc3 = &sdio1;
+ nandc0 = &nandc0;
+ nandc1 = &nandc1;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -596,6 +598,28 @@
status = "disabled";
};

+ nandc0: nand-controller@ff400000 {
+ compatible = "rockchip,nandc-v6";
+ reg = <0x0 0xff400000 0x0 0x4000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
+ clock-names = "clk_nandc", "hclk_nandc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ nandc1: nand-controller@ff410000 {
+ compatible = "rockchip,nandc-v6";
+ reg = <0x0 0xff410000 0x0 0x4000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_NANDC1>, <&cru HCLK_NANDC1>;
+ clock-names = "clk_nandc", "hclk_nandc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
usb_host0_ehci: usb@ff500000 {
compatible = "generic-ehci";
reg = <0x0 0xff500000 0x0 0x100>;
--
2.11.0
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