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SubjectRE: [PATCH V2 2/5] clk: imx: Add support for i.MX8M hw based clk provider
Date
> Subject: [PATCH V2 2/5] clk: imx: Add support for i.MX8M hw based clk
> provider
>
> Add hw based provider support for i.MX8M composite clk, pll14xx clk and
> other gate/mux clk APIs, so that new added i.MX8M SoCs can use hw based
> clk provider.

i.MX8M hw composite clk has been in shawn's tree,
https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git/
commit/?h=for-next&id=a4b431f8038a67222fde888a48bcbd704d2daca0

You might be using an old base?

Regards,
Peng.

>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> New patch.
> ---
> drivers/clk/imx/clk-composite-8m.c | 4 ++--
> drivers/clk/imx/clk-pll14xx.c | 18 +++++++++-------
> drivers/clk/imx/clk.h | 42
> +++++++++++++++++++++++++++++++++-----
> 3 files changed, 50 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/clk/imx/clk-composite-8m.c
> b/drivers/clk/imx/clk-composite-8m.c
> index d3486ee..20f7c91 100644
> --- a/drivers/clk/imx/clk-composite-8m.c
> +++ b/drivers/clk/imx/clk-composite-8m.c
> @@ -123,7 +123,7 @@ static const struct clk_ops
> imx8m_clk_composite_divider_ops = {
> .set_rate = imx8m_clk_composite_divider_set_rate,
> };
>
> -struct clk *imx8m_clk_composite_flags(const char *name,
> +struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
> const char * const *parent_names,
> int num_parents, void __iomem *reg,
> unsigned long flags)
> @@ -171,7 +171,7 @@ struct clk *imx8m_clk_composite_flags(const char
> *name,
> if (IS_ERR(hw))
> goto fail;
>
> - return hw->clk;
> + return hw;
>
> fail:
> kfree(gate);
> diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index
> e238427..db12fb6 100644
> --- a/drivers/clk/imx/clk-pll14xx.c
> +++ b/drivers/clk/imx/clk-pll14xx.c
> @@ -376,14 +376,15 @@ static const struct clk_ops clk_pll1443x_ops = {
> .set_rate = clk_pll1443x_set_rate,
> };
>
> -struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
> +struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char
> +*parent_name,
> void __iomem *base,
> const struct imx_pll14xx_clk *pll_clk) {
> struct clk_pll14xx *pll;
> - struct clk *clk;
> + struct clk_hw *hw;
> struct clk_init_data init;
> u32 val;
> + int ret;
>
> pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> if (!pll)
> @@ -415,16 +416,19 @@ struct clk *imx_clk_pll14xx(const char *name,
> const char *parent_name,
> pll->rate_table = pll_clk->rate_table;
> pll->rate_count = pll_clk->rate_count;
>
> + hw = &pll->hw;
> +
> val = readl_relaxed(pll->base + GNRL_CTL);
> val &= ~BYPASS_MASK;
> writel_relaxed(val, pll->base + GNRL_CTL);
>
> - clk = clk_register(NULL, &pll->hw);
> - if (IS_ERR(clk)) {
> - pr_err("%s: failed to register pll %s %lu\n",
> - __func__, name, PTR_ERR(clk));
> + ret = clk_hw_register(NULL, hw);
> + if (ret) {
> + pr_err("%s: failed to register pll %s %d\n",
> + __func__, name, ret);
> kfree(pll);
> + return ERR_PTR(ret);
> }
>
> - return clk;
> + return hw;
> }
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index
> afc7947..90f9ab8 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -123,8 +123,13 @@ extern struct imx_pll14xx_clk imx_1443x_dram_pll;
> bypass1, bypass2, base, flags) \
> to_clk(imx_clk_hw_sscg_pll(name, parent_names, num_parents,
> parent,\
> bypass1, bypass2, base, flags))
> +#define imx_clk_pll14xx(name, parent_name, base, pll_clk) \
> + to_clk(imx_clk_hw_pll14xx(name, parent_name, base, pll_clk))
>
> -struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
> +#define imx8m_clk_composite_flags(name, parent_names, num_parents,
> reg, flags) \
> + to_clk(imx8m_clk_hw_composite_flags(name, parent_names,
> num_parents,
> +reg, flags))
> +
> +struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char
> +*parent_name,
> void __iomem *base, const struct imx_pll14xx_clk *pll_clk);
>
> struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char
> *name, @@ -388,6 +393,14 @@ static inline struct clk
> *imx_clk_gate4_flags(const char *name,
> reg, shift, 0x3, 0, &imx_ccm_lock, NULL); }
>
> +static inline struct clk_hw *imx_clk_hw_gate4_flags(const char *name, const
> char *parent,
> + void __iomem *reg, u8 shift, unsigned long flags) {
> + return clk_hw_register_gate2(NULL, name, parent,
> + flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
> + reg, shift, 0x3, 0, &imx_ccm_lock, NULL); }
> +
> static inline struct clk_hw *imx_clk_hw_mux(const char *name, void
> __iomem *reg,
> u8 shift, u8 width, const char * const *parents,
> int num_parents)
> @@ -437,6 +450,15 @@ static inline struct clk *imx_clk_mux2_flags(const
> char *name,
> reg, shift, width, 0, &imx_ccm_lock); }
>
> +static inline struct clk_hw *imx_clk_hw_mux2_flags(const char *name, void
> __iomem *reg,
> + u8 shift, u8 width, const char * const *parents,
> + int num_parents, unsigned long flags) {
> + return clk_hw_register_mux(NULL, name, parents, num_parents,
> + flags | CLK_SET_RATE_NO_REPARENT |
> CLK_OPS_PARENT_ENABLE,
> + reg, shift, width, 0, &imx_ccm_lock); }
> +
> static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name,
> void __iomem *reg, u8 shift,
> u8 width,
> @@ -453,10 +475,9 @@ struct clk_hw *imx_clk_hw_cpu(const char *name,
> const char *parent_name,
> struct clk *div, struct clk *mux, struct clk *pll,
> struct clk *step);
>
> -struct clk *imx8m_clk_composite_flags(const char *name,
> - const char * const *parent_names,
> - int num_parents, void __iomem *reg,
> - unsigned long flags);
> +struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
> + const char * const *parent_names, int num_parents,
> + void __iomem *reg, unsigned long flags);
>
> #define __imx8m_clk_composite(name, parent_names, reg, flags) \
> imx8m_clk_composite_flags(name, parent_names, \ @@ -469,6 +490,17
> @@ struct clk *imx8m_clk_composite_flags(const char *name, #define
> imx8m_clk_composite_critical(name, parent_names, reg) \
> __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
>
> +#define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \
> + imx8m_clk_hw_composite_flags(name, parent_names, \
> + ARRAY_SIZE(parent_names), reg, \
> + flags | CLK_SET_RATE_NO_REPARENT |
> CLK_OPS_PARENT_ENABLE)
> +
> +#define imx8m_clk_hw_composite(name, parent_names, reg) \
> + __imx8m_clk_hw_composite(name, parent_names, reg, 0)
> +
> +#define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
> + __imx8m_clk_hw_composite(name, parent_names, reg,
> CLK_IS_CRITICAL)
> +
> struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char
> *parent_name,
> unsigned long flags, void __iomem *reg, u8 shift, u8 width,
> u8 clk_divider_flags, const struct clk_div_table *table,
> --
> 2.7.4

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