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SubjectRe: [v3] x86/tsc: Unset TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Bay Trail SoC
On Wed, Jan 29, 2020 at 02:21:40PM +0100, Hans de Goede wrote:
> On 29-01-2020 14:03, Andy Shevchenko wrote:
> > On Tue, Jan 28, 2020 at 11:39:28PM +0100, Thomas Gleixner wrote:
> > > Hans de Goede <hdegoede@redhat.com> writes:

...

> > > Typical crystal frequencies are 19.2, 24 and 25Mhz.
> >
> > Hans, I think Cherrytrail may be affected by this as the others.
> > CHT AFAIK uses 19.2MHz xtal.
>
> Are you sure?

I'm not. I may mixed this with PMC clock.

> The first 5 entries of the CHT MSR_FSB_FREQ documentation exactly
> match those of the BYT documentation (which has only 5 entries),
> which suggests to me that CHT is also using a 25 MHz crystal.
>
> I can also make the other CHT only frequencies when assuming a 25
> MHz crystal, here is a bit from the patch I'm working on for this:
>
> /*
> * Cherry Trail SDM MSR_FSB_FREQ frequencies to PLL settings map:
> * 0000: 25 * 20 / 6 = 83.3333 MHz
> * 0001: 25 * 4 / 1 = 100.0000 MHz
> * 0010: 25 * 16 / 3 = 133.3333 MHz
> * 0011: 25 * 28 / 6 = 116.6667 MHz
> * 0100: 25 * 16 / 5 = 80.0000 MHz
> * 0101: 25 * 56 / 15 = 93.3333 MHz
> * 0110: 25 * 18 / 5 = 90.0000 MHz
> * 0111: 25 * 32 / 9 = 88.8889 MHz
> * 1000: 25 * 7 / 2 = 87.5000 MHz
> */
>
> The only one which is possibly suspicious here is this line:
>
> * 0111: 25 * 32 / 9 = 88.8889 MHz
>
> The SDM says 88.9 MHz for this one.

Anyway it seems need to be fixed as well.

Btw, why we are mentioning 20 / 6 and 28 / 6 when arithmetically
it's the same as 10 / 3 and 14 / 3?

--
With Best Regards,
Andy Shevchenko


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