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    Subject[PATCH 4.19 276/639] net: phy: dont clear BMCR in genphy_soft_reset
    Date
    From: Heiner Kallweit <hkallweit1@gmail.com>

    [ Upstream commit d29f5aa0bc0c321e1b9e4658a2a7e08e885da52a ]

    So far we effectively clear the BMCR register. Some PHY's can deal
    with this (e.g. because they reset BMCR to a default as part of a
    soft-reset) whilst on others this causes issues because e.g. the
    autoneg bit is cleared. Marvell is an example, see also thread [0].
    So let's be a little bit more gentle and leave all bits we're not
    interested in as-is. This change is needed for PHY drivers to
    properly deal with the original patch.

    [0] https://marc.info/?t=155264050700001&r=1&w=2

    Fixes: 6e2d85ec0559 ("net: phy: Stop with excessive soft reset")
    Tested-by: Phil Reid <preid@electromag.com.au>
    Tested-by: liweihang <liweihang@hisilicon.com>
    Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
    Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
    Signed-off-by: David S. Miller <davem@davemloft.net>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/net/phy/phy_device.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
    index 9c7e51443f6b6..ae40d8137fd20 100644
    --- a/drivers/net/phy/phy_device.c
    +++ b/drivers/net/phy/phy_device.c
    @@ -1657,7 +1657,7 @@ int genphy_soft_reset(struct phy_device *phydev)
    {
    int ret;

    - ret = phy_write(phydev, MII_BMCR, BMCR_RESET);
    + ret = phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
    if (ret < 0)
    return ret;

    --
    2.20.1


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