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SubjectRe: [PATCH] gpio: mvebu: clear irq in edge cause register before unmask edge irq
On Wed, Jan 15, 2020 at 8:40 AM Maxim <> wrote:

> From: Maxim Kiselev <>
> When input GPIO set from 0 to 1, the interrupt bit asserted in the GPIO
> Interrupt Cause Register (ICR) even if the corresponding interrupt
> masked in the GPIO Interrupt Mask Register.
> Because interrupt mask register only affects assertion of the interrupt
> bits in Main Interrupt Cause Register and it does not affect the
> setting of bits in the GPIO ICR.
> So, there is problem, when we unmask interrupt with already
> asserted bit in the GPIO ICR, then false interrupt immediately occurs
> even if GPIO don't change their value since last unmask.
> Signed-off-by: Maxim Kiselev <>

Since there is no feedback from the MVEBU maintainers I have
tentatively applied the patch for v5.6 so it gets some testing.

Linus Walleij

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