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    Subject[PATCH 3/8] ARM: at91: pm: add macros for plla disable/enable
    Date
    Add macros for PLLA disable and enable (in disable macro the PLLA
    state will also be saved). This prepares the field for PLLA disable/enable
    for suspend/resume on SAM9X60.

    Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
    ---
    arch/arm/mach-at91/pm_suspend.S | 57 ++++++++++++++++++++++-------------------
    1 file changed, 30 insertions(+), 27 deletions(-)

    diff --git a/arch/arm/mach-at91/pm_suspend.S b/arch/arm/mach-at91/pm_suspend.S
    index bfb3aab8859e..64460b4e0fc1 100644
    --- a/arch/arm/mach-at91/pm_suspend.S
    +++ b/arch/arm/mach-at91/pm_suspend.S
    @@ -47,15 +47,6 @@ tmp2 .req r5
    .endm

    /*
    - * Wait until PLLA has locked.
    - */
    - .macro wait_pllalock
    -1: ldr tmp1, [pmc, #AT91_PMC_SR]
    - tst tmp1, #AT91_PMC_LOCKA
    - beq 1b
    - .endm
    -
    -/*
    * Put the processor to enter the idle state
    */
    .macro at91_cpu_idle
    @@ -336,6 +327,34 @@ ENDPROC(at91_backup_mode)
    3:
    .endm

    +.macro at91_plla_disable
    + /* Save PLLA setting and disable it */
    + ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
    + str tmp1, .saved_pllar
    +
    + /* Disable PLLA. */
    + mov tmp1, #AT91_PMC_PLLCOUNT
    + orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
    + str tmp1, [pmc, #AT91_CKGR_PLLAR]
    +.endm
    +
    +.macro at91_plla_enable
    + /* Restore PLLA setting */
    + ldr tmp1, .saved_pllar
    + str tmp1, [pmc, #AT91_CKGR_PLLAR]
    +
    + /* Enable PLLA. */
    + tst tmp1, #(AT91_PMC_MUL & 0xff0000)
    + bne 1f
    + tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
    + beq 2f
    +
    +1: ldr tmp1, [pmc, #AT91_PMC_SR]
    + tst tmp1, #AT91_PMC_LOCKA
    + beq 1b
    +2:
    +.endm
    +
    ENTRY(at91_ulp_mode)
    ldr pmc, .pmc_base
    ldr tmp2, .mckr_offset
    @@ -352,13 +371,7 @@ ENTRY(at91_ulp_mode)

    wait_mckrdy

    - /* Save PLLA setting and disable it */
    - ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
    - str tmp1, .saved_pllar
    -
    - mov tmp1, #AT91_PMC_PLLCOUNT
    - orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
    - str tmp1, [pmc, #AT91_CKGR_PLLAR]
    + at91_plla_disable

    ldr r0, .pm_mode
    cmp r0, #AT91_PM_ULP1
    @@ -374,17 +387,7 @@ ulp1_mode:
    ulp_exit:
    ldr pmc, .pmc_base

    - /* Restore PLLA setting */
    - ldr tmp1, .saved_pllar
    - str tmp1, [pmc, #AT91_CKGR_PLLAR]
    -
    - tst tmp1, #(AT91_PMC_MUL & 0xff0000)
    - bne 3f
    - tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
    - beq 4f
    -3:
    - wait_pllalock
    -4:
    + at91_plla_enable

    /*
    * Restore master clock setting
    --
    2.7.4
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