Messages in this thread Patch in this message | | | From | Horia Geantă <> | Subject | [PATCH v2 2/3] clk: imx8mn: add SNVS clock to clock tree | Date | Thu, 16 Jan 2020 09:37:17 +0200 |
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i.mx8mn has support for clock gating the snvs module. Add it into clock tree so that rtc-snvs driver could use it.
Note this will also be required in the snvs_pwrkey driver, once support for clock management will be added.
Signed-off-by: Horia Geantă <horia.geanta@nxp.com> --- drivers/clk/imx/clk-imx8mn.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index ce2ba3dce483..6a50b59968f5 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -519,6 +519,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5); hws[IMX8MN_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6); hws[IMX8MN_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6); + hws[IMX8MN_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0); hws[IMX8MN_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0); hws[IMX8MN_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0); hws[IMX8MN_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0); -- 2.17.1
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