Messages in this thread | | | Date | Wed, 15 Jan 2020 14:03:24 +0000 | From | Marc Zyngier <> | Subject | Re: [PATCH v2 10/18] arm64: KVM/debug: use EL1&0 stage 1 translation regime |
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On 2020-01-13 16:31, Andrew Murray wrote: > On Sun, Dec 22, 2019 at 10:34:55AM +0000, Marc Zyngier wrote: >> On Fri, 20 Dec 2019 14:30:17 +0000, >> Andrew Murray <andrew.murray@arm.com> wrote: >> > >> > From: Sudeep Holla <sudeep.holla@arm.com> >> > >> > Now that we have all the save/restore mechanism in place, lets enable >> > the translation regime used by buffer from EL2 stage 1 to EL1 stage 1 >> > on VHE systems. >> > >> > Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> >> > [ Reword commit, don't trap to EL2 ] >> >> Not trapping to EL2 for the case where we don't allow SPE in the >> guest is not acceptable. >> >> > Signed-off-by: Andrew Murray <andrew.murray@arm.com> >> > --- >> > arch/arm64/kvm/hyp/switch.c | 2 ++ >> > 1 file changed, 2 insertions(+) >> > >> > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c >> > index 67b7c160f65b..6c153b79829b 100644 >> > --- a/arch/arm64/kvm/hyp/switch.c >> > +++ b/arch/arm64/kvm/hyp/switch.c >> > @@ -100,6 +100,7 @@ static void activate_traps_vhe(struct kvm_vcpu *vcpu) >> > >> > write_sysreg(val, cpacr_el1); >> > >> > + write_sysreg(vcpu->arch.mdcr_el2 | 3 << MDCR_EL2_E2PB_SHIFT, mdcr_el2); >> > write_sysreg(kvm_get_hyp_vector(), vbar_el1); >> > } >> > NOKPROBE_SYMBOL(activate_traps_vhe); >> > @@ -117,6 +118,7 @@ static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu) >> > __activate_traps_fpsimd32(vcpu); >> > } >> > >> > + write_sysreg(vcpu->arch.mdcr_el2 | 3 << MDCR_EL2_E2PB_SHIFT, mdcr_el2); >> >> There is a _MASK macro that can replace this '3', and is in keeping >> with the rest of the code. >> >> It still remains that it looks like the wrong place to do this, and >> vcpu_load seems much better. Why should you write to mdcr_el2 on each >> entry to the guest, since you know whether it has SPE enabled at the >> point where it gets scheduled? > > For nVHE, the only reason we'd want to change E2PB on entry/exit of > guest > would be if the host is also using SPE. If the host is using SPE whilst > the vcpu is 'loaded' but we're not in the guest, then host SPE could > raise > an interrupt - we need the E2PB bits to allow access from EL1 (host).
My comment was of course for VHE. nVHE hardly makes use of load/put at all, for obvious reasons.
M. -- Jazz is not dead. It just smells funny...
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