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Subject[PATCH net-next RFC 1/3] net/mlx5: Add structure layout and defines for MFRL register
Date
Add needed structure layouts and defines for MFRL (Management Firmware
Reset Level) register. This structure will be used for the firmware
upgrade and reset flow in the downstream patches.

Signed-off-by: Moshe Shemesh <moshe@mellanox.com>
---
include/linux/mlx5/driver.h | 1 +
include/linux/mlx5/mlx5_ifc.h | 17 +++++++++++++++++
2 files changed, 18 insertions(+)

diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index 583733a..268ecfd 100644
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -130,6 +130,7 @@ enum {
MLX5_REG_NODE_DESC = 0x6001,
MLX5_REG_HOST_ENDIANNESS = 0x7004,
MLX5_REG_MCIA = 0x9014,
+ MLX5_REG_MFRL = 0x9028,
MLX5_REG_MLCR = 0x902b,
MLX5_REG_MTRC_CAP = 0x9040,
MLX5_REG_MTRC_CONF = 0x9041,
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 178757c..7684537 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -9584,6 +9584,22 @@ struct mlx5_ifc_mcda_reg_bits {
u8 data[0][0x20];
};

+enum {
+ MLX5_MFRL_REG_RESET_LEVEL0 = 0x1,
+ MLX5_MFRL_REG_RESET_LEVEL3 = 0x8,
+ MLX5_MFRL_REG_RESET_LEVEL6 = 0x40,
+};
+
+struct mlx5_ifc_mfrl_reg_bits {
+ u8 reserved_at_0[0x20];
+
+ u8 reserved_at_20[0x5];
+ u8 rst_type_sel[0x3];
+ u8 reserved_at_28[0x8];
+ u8 reset_type[0x8];
+ u8 reset_level[0x8];
+};
+
struct mlx5_ifc_mirc_reg_bits {
u8 reserved_at_0[0x18];
u8 status_code[0x8];
@@ -9646,6 +9662,7 @@ struct mlx5_ifc_mirc_reg_bits {
struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
struct mlx5_ifc_mcc_reg_bits mcc_reg;
struct mlx5_ifc_mcda_reg_bits mcda_reg;
+ struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
struct mlx5_ifc_mirc_reg_bits mirc_reg;
u8 reserved_at_0[0x60e0];
};
--
1.8.3.1
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