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SubjectRe: [PATCH 1/3] xhci: Ensure link state is U3 after setting USB_SS_PORT_LS_U3
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On 13.1.2020 11.10, Kai-Heng Feng wrote:
> On Fri, Jan 10, 2020 at 5:33 PM Mathias Nyman
> <mathias.nyman@linux.intel.com> wrote:
>>> @@ -1316,9 +1317,17 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
>>> msleep(20); /* wait device to enter */
>>> spin_lock_irqsave(&xhci->lock, flags);
>>>
>>> - temp = readl(ports[wIndex]->addr);
>>> - if (link_state == USB_SS_PORT_LS_U3)
>>> + if (link_state == USB_SS_PORT_LS_U3) {
>>> + retval = xhci_handshake(ports[wIndex]->addr, PORT_PLS_MASK, XDEV_U3, 80 * 1000);
>>> + if (retval)
>>> + xhci_dbg(xhci, "polling XDEV_U3 on port %d-%d timeout\n", hcd->self.busnum, wIndex + 1);
>>
>> In worst case we are busylooping for 80ms here, keeping the cpu busy.
>> It should be ok to sleep here, so how about just reading the register
>> every 10ms max 10 times, sleeping in between.
>
> Ok. Is the polling safe outside of spin_lock_irqsave()?
>

Should be, we only read one 32 bit register, and we anyway used to release
and re-acquire the lock right before this anyway.

-Mathias

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