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Subject[tip: x86/cpu] x86/mce: WARN once if IA32_FEAT_CTL MSR is left unlocked
The following commit has been merged into the x86/cpu branch of tip:

Commit-ID: 6d527cebfa04ba4792be9e79e0d7cab22ab6c377
Gitweb: https://git.kernel.org/tip/6d527cebfa04ba4792be9e79e0d7cab22ab6c377
Author: Sean Christopherson <sean.j.christopherson@intel.com>
AuthorDate: Fri, 20 Dec 2019 20:44:59 -08:00
Committer: Borislav Petkov <bp@suse.de>
CommitterDate: Mon, 13 Jan 2020 17:47:18 +01:00

x86/mce: WARN once if IA32_FEAT_CTL MSR is left unlocked

WARN if the IA32_FEAT_CTL MSR is somehow left unlocked now that CPU
initialization unconditionally locks the MSR.

Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20191221044513.21680-6-sean.j.christopherson@intel.com
---
arch/x86/kernel/cpu/mce/intel.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index c238518..5627b10 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -116,14 +116,15 @@ static bool lmce_supported(void)
/*
* BIOS should indicate support for LMCE by setting bit 20 in
* IA32_FEAT_CTL without which touching MCG_EXT_CTL will generate a #GP
- * fault.
+ * fault. The MSR must also be locked for LMCE_ENABLED to take effect.
+ * WARN if the MSR isn't locked as init_ia32_feat_ctl() unconditionally
+ * locks the MSR in the event that it wasn't already locked by BIOS.
*/
rdmsrl(MSR_IA32_FEAT_CTL, tmp);
- if ((tmp & (FEAT_CTL_LOCKED | FEAT_CTL_LMCE_ENABLED)) ==
- (FEAT_CTL_LOCKED | FEAT_CTL_LMCE_ENABLED))
- return true;
+ if (WARN_ON_ONCE(!(tmp & FEAT_CTL_LOCKED)))
+ return false;

- return false;
+ return tmp & FEAT_CTL_LMCE_ENABLED;
}

bool mce_intel_cmci_poll(void)
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