lkml.org 
[lkml]   [2020]   [Jan]   [14]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH v5 2/6] ARM: dts: bcm2711: Enable PCIe controller
On Mon, Dec 16, 2019 at 12:01:08PM +0100, Nicolas Saenz Julienne wrote:
> This enables bcm2711's PCIe bus, which is hardwired to a VIA
> Technologies XHCI USB 3.0 controller.
>
> Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
>
> ---
>
> Changes since v4:
> - Rebase commit taking into account genet support series
>
> Changes since v3:
> - Remove unwarranted comment
>
> Changes since v2:
> - Remove unused interrupt-map
> - correct dma-ranges to it's full size, non power of 2 bus DMA
> constraints now supported in linux-next[1]
> - add device_type
> - rename alias from pcie_0 to pcie0
>
> Changes since v1:
> - remove linux,pci-domain
>
> [1] https://lkml.org/lkml/2019/11/21/235
>
> arch/arm/boot/dts/bcm2711.dtsi | 31 ++++++++++++++++++++++++++++++-
> 1 file changed, 30 insertions(+), 1 deletion(-)

Olof as we discussed previously, I will not merge this dts change and
drop it from the series - Nicolas should redirect it to arm-soc, please
let me know if my understanding is correct.

Thanks,
Lorenzo

> diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
> index e2f6ffb00aa9..b56388ce1216 100644
> --- a/arch/arm/boot/dts/bcm2711.dtsi
> +++ b/arch/arm/boot/dts/bcm2711.dtsi
> @@ -331,7 +331,36 @@ scb {
> #address-cells = <2>;
> #size-cells = <1>;
>
> - ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>;
> + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
> + <0x6 0x00000000 0x6 0x00000000 0x40000000>;
> +
> + pcie0: pcie@7d500000 {
> + compatible = "brcm,bcm2711-pcie";
> + reg = <0x0 0x7d500000 0x9310>;
> + device_type = "pci";
> + #address-cells = <3>;
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "pcie", "msi";
> + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
> + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
> + IRQ_TYPE_LEVEL_HIGH>;
> + msi-controller;
> + msi-parent = <&pcie0>;
> +
> + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
> + 0x0 0x04000000>;
> + /*
> + * The wrapper around the PCIe block has a bug
> + * preventing it from accessing beyond the first 3GB of
> + * memory.
> + */
> + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
> + 0x0 0xc0000000>;
> + brcm,enable-ssc;
> + };
>
> genet: ethernet@7d580000 {
> compatible = "brcm,bcm2711-genet-v5";
> --
> 2.24.0
>

\
 
 \ /
  Last update: 2020-01-14 19:12    [W:0.147 / U:0.232 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site