Messages in this thread | | | Date | Fri, 10 Jan 2020 17:30:45 -0800 (PST) | From | Paul Walmsley <> | Subject | Re: [PATCH 1/2] riscv: Fixup obvious bug for fp-regs reset |
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On Sun, 5 Jan 2020, guoren@kernel.org wrote:
> From: Guo Ren <ren_guo@c-sky.com> > > CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine > ISA Register misa. Every bit:1 indicate a feature, so we should beqz > reset_done when there is no F/D bit in csr_msia register. > > Signed-off-by: Guo Ren <ren_guo@c-sky.com>
Thanks Guo Ren, queued for v5.5-rc.
- Paul
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