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Subject[PATCH 3/3] arm64: dts: imx8mm: properly describe IRQ hierarchy
Date
The GPCv2 sits between most of the peripherals and the GIC and
functions as a wakeup controller for the CPU cores. Add already
two power domains. Those domains was tested on imx8mm board

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 31 ++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 6edbdfe2d0d7..7360dc0685eb 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -4,6 +4,7 @@
*/

#include <dt-bindings/clock/imx8mm-clock.h>
+#include <dt-bindings/power/imx8mm-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -12,7 +13,7 @@
#include "imx8mm-pinfunc.h"

/ {
- interrupt-parent = <&gic>;
+ interrupt-parent = <&gpc>;
#address-cells = <2>;
#size-cells = <2>;

@@ -197,6 +198,7 @@
interrupts = <GIC_PPI 7
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
+ interrupt-parent = <&gic>;
};

timer {
@@ -206,6 +208,7 @@
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
clock-frequency = <8000000>;
+ interrupt-parent = <&gic>;
arm,no-tick-in-suspend;
};

@@ -498,6 +501,29 @@
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
+
+ gpc: gpc@303a0000 {
+ compatible = "fsl,imx8mm-gpc";
+ reg = <0x303a0000 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pgc_otg1: power-domain@2 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_USB_OTG1>;
+ };
+
+ pgc_otg2: power-domain@3 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MM_POWER_DOMAIN_USB_OTG2>;
+ };
+ };
+ };
};

aips2: bus@30400000 {
@@ -790,6 +816,7 @@
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
fsl,usbphy = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
+ power-domains = <&pgc_otg1>;
status = "disabled";
};

@@ -809,6 +836,7 @@
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
fsl,usbphy = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
+ power-domains = <&pgc_otg2>;
status = "disabled";
};

@@ -856,6 +884,7 @@
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
};

ddr-pmu@3d800000 {
--
2.17.1
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