Messages in this thread Patch in this message | | | Date | Fri, 06 Sep 2019 11:08:17 -0000 | From | "tip-bot2 for Marc Zyngier" <> | Subject | [tip: irq/core] dt-bindings: interrupt-controller: arm,gic-v3: Describe ESPI range support |
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The following commit has been merged into the irq/core branch of tip:
Commit-ID: 866246534836c60f706076cdefcd45072ad9eab2 Gitweb: https://git.kernel.org/tip/866246534836c60f706076cdefcd45072ad9eab2 Author: Marc Zyngier <maz@kernel.org> AuthorDate: Tue, 16 Jul 2019 15:18:40 +01:00 Committer: Marc Zyngier <maz@kernel.org> CommitterDate: Tue, 20 Aug 2019 10:04:09 +01:00
dt-bindings: interrupt-controller: arm,gic-v3: Describe ESPI range support
GICv3.1 introduces support for new interrupt ranges, one of them being the Extended SPI range (ESPI). The DT binding is extended to deal with it as a new interrupt class.
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Marc Zyngier <maz@kernel.org> --- Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml index c34df35..98a3ecd 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml @@ -44,11 +44,12 @@ properties: be at least 4. The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI - interrupts. Other values are reserved for future use. + interrupts, 2 for interrupts in the Extended SPI range. Other values + are reserved for future use. The 2nd cell contains the interrupt number for the interrupt type. SPI interrupts are in the range [0-987]. PPI interrupts are in the - range [0-15]. + range [0-15]. Extented SPI interrupts are in the range [0-1023]. The 3rd cell is the flags, encoded as follows: bits[3:0] trigger type and level flags.
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