lkml.org 
[lkml]   [2019]   [Sep]   [3]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v3 14/14] arm64: dts: mediatek: Get rid of mediatek,larb for MM nodes
    Date
    After adding device_link between the IOMMU consumer and smi,
    the mediatek,larb is unnecessary now.

    CC: Matthias Brugger <matthias.bgg@gmail.com>
    Signed-off-by: Yong Wu <yong.wu@mediatek.com>
    Reviewed-by: Evan Green <evgreen@chromium.org>
    ---
    arch/arm64/boot/dts/mediatek/mt8173.dtsi | 15 ---------------
    1 file changed, 15 deletions(-)

    diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
    index 15f1842..06e2c09 100644
    --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
    +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
    @@ -921,7 +921,6 @@
    <&mmsys CLK_MM_MUTEX_32K>;
    power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
    iommus = <&iommu M4U_PORT_MDP_RDMA0>;
    - mediatek,larb = <&larb0>;
    mediatek,vpu = <&vpu>;
    };

    @@ -932,7 +931,6 @@
    <&mmsys CLK_MM_MUTEX_32K>;
    power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
    iommus = <&iommu M4U_PORT_MDP_RDMA1>;
    - mediatek,larb = <&larb4>;
    };

    mdp_rsz0: rsz@14003000 {
    @@ -962,7 +960,6 @@
    clocks = <&mmsys CLK_MM_MDP_WDMA>;
    power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
    iommus = <&iommu M4U_PORT_MDP_WDMA>;
    - mediatek,larb = <&larb0>;
    };

    mdp_wrot0: wrot@14007000 {
    @@ -971,7 +968,6 @@
    clocks = <&mmsys CLK_MM_MDP_WROT0>;
    power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
    iommus = <&iommu M4U_PORT_MDP_WROT0>;
    - mediatek,larb = <&larb0>;
    };

    mdp_wrot1: wrot@14008000 {
    @@ -980,7 +976,6 @@
    clocks = <&mmsys CLK_MM_MDP_WROT1>;
    power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
    iommus = <&iommu M4U_PORT_MDP_WROT1>;
    - mediatek,larb = <&larb4>;
    };

    ovl0: ovl@1400c000 {
    @@ -990,7 +985,6 @@
    power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
    clocks = <&mmsys CLK_MM_DISP_OVL0>;
    iommus = <&iommu M4U_PORT_DISP_OVL0>;
    - mediatek,larb = <&larb0>;
    };

    ovl1: ovl@1400d000 {
    @@ -1000,7 +994,6 @@
    power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
    clocks = <&mmsys CLK_MM_DISP_OVL1>;
    iommus = <&iommu M4U_PORT_DISP_OVL1>;
    - mediatek,larb = <&larb4>;
    };

    rdma0: rdma@1400e000 {
    @@ -1010,7 +1003,6 @@
    power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
    clocks = <&mmsys CLK_MM_DISP_RDMA0>;
    iommus = <&iommu M4U_PORT_DISP_RDMA0>;
    - mediatek,larb = <&larb0>;
    };

    rdma1: rdma@1400f000 {
    @@ -1020,7 +1012,6 @@
    power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
    clocks = <&mmsys CLK_MM_DISP_RDMA1>;
    iommus = <&iommu M4U_PORT_DISP_RDMA1>;
    - mediatek,larb = <&larb4>;
    };

    rdma2: rdma@14010000 {
    @@ -1030,7 +1021,6 @@
    power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
    clocks = <&mmsys CLK_MM_DISP_RDMA2>;
    iommus = <&iommu M4U_PORT_DISP_RDMA2>;
    - mediatek,larb = <&larb4>;
    };

    wdma0: wdma@14011000 {
    @@ -1040,7 +1030,6 @@
    power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
    clocks = <&mmsys CLK_MM_DISP_WDMA0>;
    iommus = <&iommu M4U_PORT_DISP_WDMA0>;
    - mediatek,larb = <&larb0>;
    };

    wdma1: wdma@14012000 {
    @@ -1050,7 +1039,6 @@
    power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
    clocks = <&mmsys CLK_MM_DISP_WDMA1>;
    iommus = <&iommu M4U_PORT_DISP_WDMA1>;
    - mediatek,larb = <&larb4>;
    };

    color0: color@14013000 {
    @@ -1294,7 +1282,6 @@
    <0 0x16027800 0 0x800>, /* VDEC_HWB */
    <0 0x16028400 0 0x400>; /* VDEC_HWG */
    interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
    - mediatek,larb = <&larb1>;
    iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
    <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
    <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
    @@ -1364,8 +1351,6 @@
    <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
    interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
    <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
    - mediatek,larb = <&larb3>,
    - <&larb5>;
    iommus = <&iommu M4U_PORT_VENC_RCPU>,
    <&iommu M4U_PORT_VENC_REC>,
    <&iommu M4U_PORT_VENC_BSDMA>,
    --
    1.9.1
    \
     
     \ /
      Last update: 2019-09-03 11:40    [W:4.026 / U:0.156 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site