Messages in this thread | | | Subject | Re: [PATCH] drm/omap: Migrate minimum FCK/PCK ratio from Kconfig to dts | From | Tero Kristo <> | Date | Fri, 27 Sep 2019 18:37:35 +0300 |
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On 27/09/2019 16:47, Tomi Valkeinen wrote: > On 27/09/2019 15:33, Adam Ford wrote: > >>> It looks like a bug in omap clock handling. >>> >>> DSS uses dss1_alwon_fck_3430es2 as fclk. dss1_alwon_fck_3430es2 comes >>> from dpll4_ck, and there's a divider after the PLL, dpll4_m4_ck. >>> >>> When the DSS driver sets dss1_alwon_fck_3430es2 rate to 27000000 or >>> 27870967, which can be created with m4 dividers 32 and 31, it looks like >>> the divider goes to bypass, or to a very small value. DSS gets a very >>> high clock rate and breaks down. >> >> Is there anything I can do to help troubleshoot this? I could insert >> a hack that checks if we're omap3 and if so make the divider equal to >> 4, but that seems like just a hack. >> I can run more tests or insert code somewhere if you want. > > I think it's up to someone who's knowledgeable in omap clock framework. > I'm kind of hoping that Tero or Tony would be willing to debug =). I can > try to find time to debug the omap clk framework, but I'll be going on > blindly there.
If you can provide details about what clock framework / driver does wrong (sample clk_set_xyz call sequence, expected results via clk_get_xyz, and what fails), I can take a look at it. Just reporting arbitrary display driver issues I won't be able to debug at all (I don't have access to any of the displays, nor do I want to waste time debugging them without absolutely no knowledge whatsoever.)
-Tero -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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