lkml.org 
[lkml]   [2019]   [Sep]   [27]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: [PATCH 6/7] clk: meson: axg-audio: provide clk top signal name
From
Date
On 27/09/2019 11:14, Neil Armstrong wrote:
> On 24/09/2019 17:33, Jerome Brunet wrote:
>> The peripheral clock on the sm1 goes through some muxes
>> and dividers before reaching the audio gates. To model that,
>> without repeating our self too much, the "top" clock signal
>> is introduced and will serve as a the parent of the gates.
>>
>> On the axg and g12a, the top clock is just a pass-through to
>> the audio peripheral clock provided by the main controller.
>>
>> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
>> ---
>> drivers/clk/meson/axg-audio.c | 19 ++++++++++++++++---
>> drivers/clk/meson/axg-audio.h | 3 ++-
>> 2 files changed, 18 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
>> index ce8836776d1c..a8ccdbaecae2 100644
>> --- a/drivers/clk/meson/axg-audio.c
>> +++ b/drivers/clk/meson/axg-audio.c
>> @@ -74,9 +74,7 @@
>> .hw.init = &(struct clk_init_data) { \
>> .name = "aud_"#_name, \
>> .ops = &clk_regmap_gate_ops, \
>> - .parent_data = &(const struct clk_parent_data) { \
>> - .fw_name = "pclk", \
>> - }, \
>> + .parent_names = (const char *[]){ "aud_top" }, \
>> .num_parents = 1, \
>> }, \
>> }
>> @@ -504,6 +502,19 @@ static struct clk_regmap tdmout_c_lrclk =
>> AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
>>
>> /* AXG/G12A Clocks */
>> +
>> +static struct clk_hw axg_aud_top = {
>> + .init = &(struct clk_init_data) {
>> + /* Provide aud_top signal name on axg and g12a */
>> + .name = "aud_top",
>> + .ops = &(const struct clk_ops) {},
>> + .parent_data = &(const struct clk_parent_data) {
>> + .fw_name = "pclk",
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> static struct clk_regmap mst_a_mclk_sel =
>> AUD_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
>> static struct clk_regmap mst_b_mclk_sel =
>> @@ -691,6 +702,7 @@ static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
>> [AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
>> [AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
>> [AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
>> + [AUD_CLKID_TOP] = &axg_aud_top,
>> [NR_CLKS] = NULL,
>> },
>> .num = NR_CLKS,
>> @@ -835,6 +847,7 @@ static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
>> [AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw,
>> [AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
>> [AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
>> + [AUD_CLKID_TOP] = &axg_aud_top,
>> [NR_CLKS] = NULL,
>> },
>> .num = NR_CLKS,
>> diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
>> index c00e28b2e1a9..a4956837f597 100644
>> --- a/drivers/clk/meson/axg-audio.h
>> +++ b/drivers/clk/meson/axg-audio.h
>> @@ -116,9 +116,10 @@
>> #define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153
>> #define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154
>>
>> +
>
> AUD_CLKID_TOP seems to be missing here

Oh, yes it was exposed, do you need to it to be exposed since it's dummy for G12A ?

Neil

>
>
>> /* include the CLKIDs which are part of the DT bindings */
>> #include <dt-bindings/clock/axg-audio-clkc.h>
>>
>> -#define NR_CLKS 163
>> +#define NR_CLKS 164
>>
>> #endif /*__AXG_AUDIO_CLKC_H */
>>
>

\
 
 \ /
  Last update: 2019-09-27 11:37    [W:0.056 / U:3.332 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site