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SubjectRe: [PATCH v1 1/2] clk: intel: Add CGU clock driver for a new SoC
On Mon, Sep 02, 2019 at 03:20:30PM +0300, Andy Shevchenko wrote:
> On Mon, Sep 02, 2019 at 03:43:13PM +0800, Tanwar, Rahul wrote:
> > On 28/8/2019 11:09 PM, Andy Shevchenko wrote:
> > > On Wed, Aug 28, 2019 at 03:00:17PM +0800, Rahul Tanwar wrote:

> > > Does val == 0 follows the table, i.e. makes div == 1?
> >
> > 0 val means output clock is ref clock i.e. div ==1. Agree that adding
> > .val = 0, .div =1 entry will make it more clear & complete.
> >
> > > > + { .val = 0, .div = 1 },
> > > > + { .val = 1, .div = 2 },
> > > > + { .val = 2, .div = 3 },
>
> 1
>
> > > > + { .val = 3, .div = 4 },
> > > > + { .val = 4, .div = 5 },
> > > > + { .val = 5, .div = 6 },
>
> 1
>
> > > > + { .val = 6, .div = 8 },
> > > > + { .val = 7, .div = 10 },
> > > > + { .val = 8, .div = 12 },
>
> 2
>
> > > > + { .val = 9, .div = 16 },
> > > > + { .val = 10, .div = 20 },
> > > > + { .val = 11, .div = 24 },
>
> 4
>
> > > > + { .val = 12, .div = 32 },
> > > > + { .val = 13, .div = 40 },
> > > > + { .val = 14, .div = 48 },
>
> 8
>
> > > > + { .val = 15, .div = 64 },
>
> 16
>
>
> So, now we see the pattern:
>
> div = val < 3 ? (val + 1) : (1 << ((val - 3) / 3));

It's not complete, but I think you got the idea.

> So, can we eliminate table?

--
With Best Regards,
Andy Shevchenko


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