Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL
Date
Tue, 17 Sep 2019 22:00:40 -0700
Quoting Eugen.Hristev@microchip.com (2019-09-10 23:39:20) > From: Eugen Hristev <eugen.hristev@microchip.com> > > The PLL input range needs to be able to allow 24 Mhz crystal as input > Update the range accordingly in plla characteristics struct > > Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> > ---