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SubjectRe: [v4 2/2] clk: ls1028a: Add clock driver for Display output interface
Date
Quoting Wen He (2019-08-29 03:59:19)
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 801fa1cd0321..ab05f342af04 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -223,6 +223,16 @@ config CLK_QORIQ
> This adds the clock driver support for Freescale QorIQ platforms
> using common clock framework.
>
> +config CLK_LS1028A_PLLDIG
> + bool "Clock driver for LS1028A Display output"

Is this a tristate? The driver is made to be a module but it isn't
allowed to be compiled as such.

> + depends on ARCH_LAYERSCAPE || COMPILE_TEST
> + default ARCH_LAYERSCAPE
> + help
> + This driver support the Display output interfaces(LCD, DPHY) pixel clocks
> + of the QorIQ Layerscape LS1028A, as implemented TSMC CLN28HPM PLL. Not all
> + features of the PLL are currently supported by the driver. By default,
> + configured bypass mode with this PLL.
> +
> config COMMON_CLK_XGENE
> bool "Clock driver for APM XGene SoC"
> default ARCH_XGENE
> diff --git a/drivers/clk/clk-plldig.c b/drivers/clk/clk-plldig.c
> new file mode 100644
> index 000000000000..d3239bcf59de
> --- /dev/null
> +++ b/drivers/clk/clk-plldig.c
> @@ -0,0 +1,298 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2019 NXP
> + *
> + * Clock driver for LS1028A Display output interfaces(LCD, DPHY).
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/device.h>
> +#include <linux/module.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +/* PLLDIG register offsets and bit masks */
> +#define PLLDIG_REG_PLLSR 0x24
> +#define PLLDIG_REG_PLLDV 0x28
> +#define PLLDIG_REG_PLLFM 0x2c
> +#define PLLDIG_REG_PLLFD 0x30
> +#define PLLDIG_REG_PLLCAL1 0x38
> +#define PLLDIG_REG_PLLCAL2 0x3c
> +#define PLLDIG_LOCK_MASK BIT(2)
> +#define PLLDIG_SSCGBYP_ENABLE BIT(30)
> +#define PLLDIG_FDEN BIT(30)
> +#define PLLDIG_DTHRCTL (0x3 << 16)
> +
> +/* macro to get/set values into register */
> +#define PLLDIG_GET_MULT(x) (((x) & ~(0xffffff00)) << 0)
> +#define PLLDIG_GET_RFDPHI1(x) ((u32)(x) >> 25)
> +#define PLLDIG_SET_RFDPHI1(x) ((u32)(x) << 25)

Maybe you can use the FIELD_GET() APIs and genmask from bitfield.h?

> +
> +/* Maximum of the divider */
> +#define MAX_RFDPHI1 63
> +
> +/* Best value of multiplication factor divider */
> +#define PLLDIG_DEFAULE_MULT 44
> +
> +/*
> + * Clock configuration relationship between the PHI1 frequency(fpll_phi) and
> + * the output frequency of the PLL is determined by the PLLDV, according to
> + * the following equation:
> + * fpll_phi = (pll_ref * mfd) / div_rfdphi1
> + */
> +struct plldig_phi1_param {
> + unsigned long rate;
> + unsigned int rfdphi1;
> + unsigned int mfd;
> +};
> +
> +enum plldig_phi1_freq_range {
> + PHI1_MIN = 27000000U,
> + PHI1_MAX = 600000000U
> +};

Please just inline these values in the one place they're used.

> +
> +struct clk_plldig {
> + struct clk_hw hw;
> + void __iomem *regs;
> + struct device *dev;

Please remove this, it is unused.

> +};
> +
> +#define to_clk_plldig(_hw) container_of(_hw, struct clk_plldig, hw)
> +#define LOCK_TIMEOUT_US USEC_PER_MSEC

Is this used?

> +
> +static int plldig_enable(struct clk_hw *hw)
> +{
> + struct clk_plldig *data = to_clk_plldig(hw);
> + u32 val;
> +
> + val = readl(data->regs + PLLDIG_REG_PLLFM);
> + /*
> + * Use Bypass mode with PLL off by default, the frequency overshoot
> + * detector output was disable. SSCG Bypass mode should be enable.
> + */
> + val |= PLLDIG_SSCGBYP_ENABLE;
> + writel(val, data->regs + PLLDIG_REG_PLLFM);
> +
> + val = readl(data->regs + PLLDIG_REG_PLLFD);
> + /* Disable dither and Sigma delta modulation in bypass mode */
> + val |= (PLLDIG_FDEN | PLLDIG_DTHRCTL);
> + writel(val, data->regs + PLLDIG_REG_PLLFD);
> +
> + return 0;
> +}
> +
> +static void plldig_disable(struct clk_hw *hw)
> +{
> + struct clk_plldig *data = to_clk_plldig(hw);
> + u32 val;
> +
> + val = readl(data->regs + PLLDIG_REG_PLLFM);
> +
> + val &= ~PLLDIG_SSCGBYP_ENABLE;
> + writel(val, data->regs + PLLDIG_REG_PLLFM);
> +}
> +
> +static int plldig_is_enabled(struct clk_hw *hw)
> +{
> + struct clk_plldig *data = to_clk_plldig(hw);
> +
> + return (readl(data->regs + PLLDIG_REG_PLLFM) & PLLDIG_SSCGBYP_ENABLE);
> +}
> +
> +static unsigned long plldig_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct clk_plldig *data = to_clk_plldig(hw);
> + u32 mult, div, val;
> +
> + val = readl(data->regs + PLLDIG_REG_PLLDV);
> +
> + /* Check if PLL is bypassed */
> + if (val & PLLDIG_SSCGBYP_ENABLE)
> + return parent_rate;
> +
> + /* Checkout multiplication factor divider value */
> + mult = val;
> + mult = PLLDIG_GET_MULT(mult);
> +
> + /* Checkout divider value of the output frequency */
> + div = val;
> + div = PLLDIG_GET_RFDPHI1(div);
> +
> + return (parent_rate * mult) / div;
> +}
> +
> +static int plldig_calc_target_rate(unsigned long target_rate,
> + unsigned long parent_rate,
> + struct plldig_phi1_param *phi1_out)
> +{
> + unsigned int div, mfd, ret;
> + unsigned long round_rate;
> +
> + /*
> + * Firstly, check the target rate whether is divisible
> + * by the best VCO frequency.
> + */
> + mfd = PLLDIG_DEFAULE_MULT;
> + round_rate = parent_rate * mfd;
> + div = round_rate / target_rate;
> + if (!div || div > MAX_RFDPHI1)
> + return -EINVAL;
> +
> + ret = round_rate % target_rate;
> + if (!ret)
> + goto out;

Please get rid of ret and do the test here directly and then put the
below code into the if statement to remove the goto.


if (round_rate % target_rate) {
/*
* Otherwise, try a rounding algorithm to driven the target rate,
* this algorithm allows tolerances between the target rate and
* real rate, it based on the best VCO output frequency.
*/
mfd = PLLDIG_DEFAULE_MULT;
round_rate = parent_rate * mfd;

/*
* Add half of the target rate so the result will be
* rounded to cloeset instead of rounded down.
*/
round_rate += (target_rate / 2);
div = round_rate / target_rate;
if (!div || div > MAX_RFDPHI1)
return -EINVAL;

}

> + phi1_out->rfdphi1 = PLLDIG_SET_RFDPHI1(div);
> + phi1_out->mfd = mfd;
> + phi1_out->rate = target_rate;
> +
> + return 0;
> +}
> +
> +static int plldig_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + int ret;
> + struct clk_hw *parent;
> + struct plldig_phi1_param phi1_param;
> + unsigned long parent_rate;
> +
> + if (req->rate == 0 || req->rate < PHI1_MIN || req->rate > PHI1_MAX)
> + return -EINVAL;

Preferably you clamp the requested rate to min/max instead of just
returning a failure. That way the clk_set_rate() API "works" by trying
to achieve some frequency that is there. You'll have to look at the
request that is passed into this function to make sure that the min/max
of the request is within the range this clk supports, but it will be
better than just blindly returning a failure because this function
should try to round the rate to something that is supported.

> +
> + parent = clk_hw_get_parent(hw);
> + parent_rate = clk_hw_get_rate(parent);
> +
> + ret = plldig_calc_target_rate(req->rate, parent_rate, &phi1_param);
> + if (ret)
> + return ret;
> +
> + req->rate = phi1_param.rate;
> +
> + return 0;
> +}
> +
> +static int plldig_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct clk_plldig *data = to_clk_plldig(hw);
> + struct plldig_phi1_param phi1_param;
> + unsigned int rfdphi1, val, cond;
> + int ret = -ETIMEDOUT;

Drop this initial assignment please.

> +
> + ret = plldig_calc_target_rate(rate, parent_rate, &phi1_param);
> + if (ret)
> + return ret;

Because it's overwritten immediately.

> +
> + val = readl(data->regs + PLLDIG_REG_PLLDV);
> + val = phi1_param.mfd;
> + rfdphi1 = phi1_param.rfdphi1;
> + val |= rfdphi1;
> +
> + writel(val, data->regs + PLLDIG_REG_PLLDV);
> +
> + /* delay 200us make sure that old lock state is cleared */
> + udelay(200);
> +
> + /* Wait until PLL is locked or timeout (maximum 1000 usecs) */
> + ret = readl_poll_timeout_atomic(data->regs + PLLDIG_REG_PLLSR, cond,
> + cond & PLLDIG_LOCK_MASK, 0,
> + USEC_PER_MSEC);
> +
> + return ret;

Just return readl_poll_timeout_atomic(...) here.

> +}
> +
> +static const struct clk_ops plldig_clk_ops = {
> + .enable = plldig_enable,
> + .disable = plldig_disable,
> + .is_enabled = plldig_is_enabled,
> + .recalc_rate = plldig_recalc_rate,
> + .determine_rate = plldig_determine_rate,
> + .set_rate = plldig_set_rate,
> +};
> +
> +static int plldig_clk_probe(struct platform_device *pdev)
> +{
> + struct clk_plldig *data;
> + struct resource *mem;
> + struct clk_init_data init = {};
> + struct device *dev = &pdev->dev;
> + struct clk_parent_data parent_data;

Set this to = { .index = 0 }

> + int ret;
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + data->regs = devm_ioremap_resource(dev, mem);
> + if (IS_ERR(data->regs))
> + return PTR_ERR(data->regs);
> +
> + parent_data.name = of_clk_get_parent_name(dev->of_node, 0);
> + parent_data.index = 0;

And don't assign these.

> +
> + init.name = dev->of_node->name;
> + init.ops = &plldig_clk_ops;
> + init.parent_data = &parent_data;
> + init.num_parents = 1;
> +
> + data->hw.init = &init;
> + data->dev = dev;
> +
> + ret = devm_clk_hw_register(dev, &data->hw);
> + if (ret) {
> + dev_err(dev, "failed to register %s clock\n", init.name);
> + return ret;
> + }
> +
> + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &data->hw);
> + if (ret)
> + dev_err(dev, "failed adding the clock provider\n");
> +
> + return ret;

I'd prefer to just see return devm_of_clk_add_hw_provider(), but not a
big deal.

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