Messages in this thread | | | Subject | Re: [PATCH v2 1/6] powerpc: Allow flush_icache_range to work across ranges >4GB | From | Christophe Leroy <> | Date | Sat, 14 Sep 2019 09:46:47 +0200 |
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Le 03/09/2019 à 07:23, Alastair D'Silva a écrit : > From: Alastair D'Silva <alastair@d-silva.org> > > When calling flush_icache_range with a size >4GB, we were masking > off the upper 32 bits, so we would incorrectly flush a range smaller > than intended. > > This patch replaces the 32 bit shifts with 64 bit ones, so that > the full size is accounted for.
Isn't there the same issue in arch/powerpc/kernel/vdso64/cacheflush.S ?
Christophe
> > Signed-off-by: Alastair D'Silva <alastair@d-silva.org> > Cc: stable@vger.kernel.org > --- > arch/powerpc/kernel/misc_64.S | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S > index b55a7b4cb543..9bc0aa9aeb65 100644 > --- a/arch/powerpc/kernel/misc_64.S > +++ b/arch/powerpc/kernel/misc_64.S > @@ -82,7 +82,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) > subf r8,r6,r4 /* compute length */ > add r8,r8,r5 /* ensure we get enough */ > lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of cache block size */ > - srw. r8,r8,r9 /* compute line count */ > + srd. r8,r8,r9 /* compute line count */ > beqlr /* nothing to do? */ > mtctr r8 > 1: dcbst 0,r6 > @@ -98,7 +98,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) > subf r8,r6,r4 /* compute length */ > add r8,r8,r5 > lwz r9,ICACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of Icache block size */ > - srw. r8,r8,r9 /* compute line count */ > + srd. r8,r8,r9 /* compute line count */ > beqlr /* nothing to do? */ > mtctr r8 > 2: icbi 0,r6 >
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