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SubjectRe: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL
Date
On 11/09/2019 at 08:39, Eugen Hristev - M18282 wrote:
> From: Eugen Hristev <eugen.hristev@microchip.com>
>
> The PLL input range needs to be able to allow 24 Mhz crystal as input
> Update the range accordingly in plla characteristics struct
>
> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Thanks Eugen!

Best regards,
Nicolas

> ---
> drivers/clk/at91/sama5d2.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
> index 6509d09..0de1108 100644
> --- a/drivers/clk/at91/sama5d2.c
> +++ b/drivers/clk/at91/sama5d2.c
> @@ -21,7 +21,7 @@ static const struct clk_range plla_outputs[] = {
> };
>
> static const struct clk_pll_characteristics plla_characteristics = {
> - .input = { .min = 12000000, .max = 12000000 },
> + .input = { .min = 12000000, .max = 24000000 },
> .num_output = ARRAY_SIZE(plla_outputs),
> .output = plla_outputs,
> .icpll = plla_icpll,
>


--
Nicolas Ferre

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