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Subject[PATCH] clk: at91: allow 24 Mhz clock as input for PLL
Date
From: Eugen Hristev <eugen.hristev@microchip.com>

The PLL input range needs to be able to allow 24 Mhz crystal as input
Update the range accordingly in plla characteristics struct

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
---
drivers/clk/at91/sama5d2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
index 6509d09..0de1108 100644
--- a/drivers/clk/at91/sama5d2.c
+++ b/drivers/clk/at91/sama5d2.c
@@ -21,7 +21,7 @@ static const struct clk_range plla_outputs[] = {
};

static const struct clk_pll_characteristics plla_characteristics = {
- .input = { .min = 12000000, .max = 12000000 },
+ .input = { .min = 12000000, .max = 24000000 },
.num_output = ARRAY_SIZE(plla_outputs),
.output = plla_outputs,
.icpll = plla_icpll,
--
2.7.4
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