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SubjectRe: [PATCH v8 18/21] soc/tegra: pmc: Configure core power request polarity
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09.08.2019 2:46, Sowjanya Komatineni пишет:
> This patch configures polarity of the core power request signal
> in PMC control register based on the device tree property.
>
> PMC asserts and de-asserts power request signal based on it polarity
> when it need to power-up and power-down the core rail during SC7.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/soc/tegra/pmc.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index 3aa71c28a10a..e013ada7e4e9 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -56,6 +56,7 @@
> #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
> #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
> #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
> +#define PMC_CNTRL_PWRREQ_POLARITY BIT(8)
> #define PMC_CNTRL_MAIN_RST BIT(4)
>
> #define PMC_WAKE_MASK 0x0c
> @@ -2290,6 +2291,11 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc)
> else
> value |= PMC_CNTRL_SYSCLK_POLARITY;
>
> + if (pmc->corereq_high)
> + value &= ~PMC_CNTRL_PWRREQ_POLARITY;
> + else
> + value |= PMC_CNTRL_PWRREQ_POLARITY;
> +
> /* configure the output polarity while the request is tristated */
> tegra_pmc_writel(pmc, value, PMC_CNTRL);
>
>

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>

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