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    Subject[PATCH 4.14 05/33] arm64: cpufeature: Fix feature comparison for CTR_EL0.{CWG,ERG}
    Date
    From: Will Deacon <will@kernel.org>

    commit 147b9635e6347104b91f48ca9dca61eb0fbf2a54 upstream.

    If CTR_EL0.{CWG,ERG} are 0b0000 then they must be interpreted to have
    their architecturally maximum values, which defeats the use of
    FTR_HIGHER_SAFE when sanitising CPU ID registers on heterogeneous
    machines.

    Introduce FTR_HIGHER_OR_ZERO_SAFE so that these fields effectively
    saturate at zero.

    Fixes: 3c739b571084 ("arm64: Keep track of CPU feature registers")
    Cc: <stable@vger.kernel.org> # 4.4.x-
    Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
    Acked-by: Mark Rutland <mark.rutland@arm.com>
    Signed-off-by: Will Deacon <will@kernel.org>
    Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/arm64/include/asm/cpufeature.h | 7 ++++---
    arch/arm64/kernel/cpufeature.c | 8 ++++++--
    2 files changed, 10 insertions(+), 5 deletions(-)

    --- a/arch/arm64/include/asm/cpufeature.h
    +++ b/arch/arm64/include/asm/cpufeature.h
    @@ -44,9 +44,10 @@
    */

    enum ftr_type {
    - FTR_EXACT, /* Use a predefined safe value */
    - FTR_LOWER_SAFE, /* Smaller value is safe */
    - FTR_HIGHER_SAFE,/* Bigger value is safe */
    + FTR_EXACT, /* Use a predefined safe value */
    + FTR_LOWER_SAFE, /* Smaller value is safe */
    + FTR_HIGHER_SAFE, /* Bigger value is safe */
    + FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */
    };

    #define FTR_STRICT true /* SANITY check strict matching required */
    --- a/arch/arm64/kernel/cpufeature.c
    +++ b/arch/arm64/kernel/cpufeature.c
    @@ -178,8 +178,8 @@ static const struct arm64_ftr_bits ftr_c
    ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
    ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1), /* DIC */
    ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1), /* IDC */
    - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */
    - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 20, 4, 0), /* ERG */
    + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 24, 4, 0), /* CWG */
    + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, 20, 4, 0), /* ERG */
    ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
    /*
    * Linux can handle differing I-cache policies. Userspace JITs will
    @@ -411,6 +411,10 @@ static s64 arm64_ftr_safe_value(const st
    case FTR_LOWER_SAFE:
    ret = new < cur ? new : cur;
    break;
    + case FTR_HIGHER_OR_ZERO_SAFE:
    + if (!cur || !new)
    + break;
    + /* Fallthrough */
    case FTR_HIGHER_SAFE:
    ret = new > cur ? new : cur;
    break;

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