Messages in this thread | | | From | Kevin Hilman <> | Subject | Re: [PATCH v2 0/4] clk: meson: g12a: add support for DVFS | Date | Thu, 08 Aug 2019 14:18:56 -0700 |
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Neil Armstrong <narmstrong@baylibre.com> writes:
> The G12A/G12B Socs embeds a specific clock tree for each CPU cluster : > cpu_clk / cpub_clk > | \- cpu_clk_dyn > | | \- cpu_clk_premux0 > | | |- cpu_clk_postmux0 > | | | |- cpu_clk_dyn0_div > | | | \- xtal/fclk_div2/fclk_div3 > | | \- xtal/fclk_div2/fclk_div3 > | \- cpu_clk_premux1 > | |- cpu_clk_postmux1 > | | |- cpu_clk_dyn1_div > | | \- xtal/fclk_div2/fclk_div3 > | \- xtal/fclk_div2/fclk_div3 > \ sys_pll / sys1_pll > > This patchset adds notifiers on cpu_clk / cpub_clk, cpu_clk_dyn, > cpu_clk_premux0 and sys_pll / sys1_pll to permit change frequency of > the CPU clock in a safe way as recommended by the vendor Documentation > and reference code. > > This patchset : > - introduces needed core and meson clk changes > - adds the clock notifiers > > Dependencies: > - None
nit: this doesn't apply to v5.3-rc, but appears to apply on clk-meson/v5.4/drivers, so it appears to be dependent on the cleanups from Alex.
Kevin
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