Messages in this thread |  | | Date | Sat, 31 Aug 2019 18:44:32 +0300 | From | Mika Westerberg <> | Subject | Re: [PATCH 2/2] mtd: spi-nor: intel-spi: add support for Intel Cannon Lake SPI flash |
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On Sat, Aug 31, 2019 at 03:29:21PM +0000, Jethro Beekman wrote: > > > + ispi->sregs = NULL; > > > + ispi->pregs = ispi->base + CNL_PR; > > > + ispi->nregions = CNL_FREG_NUM; > > > + ispi->pr_num = CNL_PR_NUM; > > > > Does CNL really have a different number of PR and FR regions than the > > previous generations? > > I'm using this as a reference: https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/300-series-chipset-pch-datasheet-vol-2.pdf > . If you have more accurate information, please let me know.
No looks correct to me. I think it is a good idea to mention this in the changelog, though.
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