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Subject[GIT PULL] RISC-V updates for v5.3-rc3
Linus,

The following changes since commit 609488bc979f99f805f34e9a32c1e3b71179d10b:

Linux 5.3-rc2 (2019-07-28 12:47:02 -0700)

are available in the Git repository at:

git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv/for-v5.3-rc3

for you to fetch changes up to b7edabfe843805b7ab8a91396b0782042a289308:

riscv: defconfig: align RV64 defconfig to the output of "make savedefconfig" (2019-07-31 12:26:10 -0700)

----------------------------------------------------------------
RISC-V updates for v5.3-rc3

Three minor RISC-V-related changes for v5.3-rc3:

- Add build ID to VDSO builds to avoid a double-free in perf when
libelf isn't used

- Align the RV64 defconfig to the output of "make savedefconfig" so
subsequent defconfig patches don't get out of hand

- Drop a superfluous DT property from the FU540 SoC DT data (since it
must be already set in board data that includes it)

----------------------------------------------------------------
Mao Han (1):
riscv: Fix perf record without libelf support

Paul Walmsley (2):
riscv: dts: fu540-c000: drop "timebase-frequency"
riscv: defconfig: align RV64 defconfig to the output of "make savedefconfig"

arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 1 -
arch/riscv/configs/defconfig | 10 +++++-----
arch/riscv/kernel/vdso/Makefile | 2 +-
3 files changed, 6 insertions(+), 7 deletions(-)

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