lkml.org 
[lkml]   [2019]   [Aug]   [28]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCH 08/15] riscv: provide native clint access for M-mode
On Tue, Aug 27, 2019 at 04:37:16PM -0700, Palmer Dabbelt wrote:
> clint0 would be version 0 of the clint, with is the core-local interrupt
> controller in rocket chip. It should be "sifive,clint-1.0.0", not
> "riscv,clint0", as it's a SiFive widget. Unfortunately there are a lot of
> legacy device trees floating around, but I'm only considering what's been
> upstream to be actually part of the spec.
>
> In this case the code should match on a "sifive,clint-1.0.0", and the
> device trees should be fixed up to match. We match on "riscv,plic0" for
> legacy systems, and I guess it makes sense to do something similar here.

IFF we decided to change it I'd rather separate DT noes for the ipi
bank vs timecmp register vs timeval to support variable layouts. The
downside is that we can't just boot on unmodified upstream qemu, which
has used the "riscv,clint0" for years.

\
 
 \ /
  Last update: 2019-08-28 08:11    [W:0.133 / U:0.032 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site