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    SubjectRe: [PATCH v2 2/2] reset: Reset controller driver for Intel LGM SoC
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    Hi Martin,

    Thanks for your comment.

    On 8/25/2019 5:11 AM, Martin Blumenstingl wrote:
    > Hi Dilip,
    >
    >> Add driver for the reset controller present on Intel
    >> Lightening Mountain (LGM) SoC for performing reset
    >> management of the devices present on the SoC. Driver also
    >> registers a reset handler to peform the entire device reset.
    > [...]
    >> +static const struct of_device_id intel_reset_match[] = {
    >> + { .compatible = "intel,rcu-lgm" },
    >> + {}
    >> +};
    > how is this IP block differnet from the one used in many Lantiq SoCs?
    > there is already an upstream driver for the RCU IP block on the Lantiq
    > SoCs: drivers/reset/reset-lantiq.c
    >
    > some background:
    > Lantiq was started as a spinoff from Infineon in 2009. Intel then
    > acquired Lantiq in 2015. source: [0]
    > Intel is re-using some of the IP blocks from the MIPS Lantiq SoCs
    > (Intel even has some own MIPS SoCs as part of the Lantiq acquisition,
    > typically used for PON/GPON/ADSL/VDSL capable network devices).
    > Thus I think it is likely that the new "Lightening Mountain" SoCs use
    > an updated version of the Lantiq RCU IP.

    I would not say there is a fundamental difference since reset is a
    really simple

    stuff from all reset drivers.  However, it did have some difference

    from existing reset-lantiq.c since SoC becomes more and more complex.

    1. reset-lantiq.c use index instead of register offset + bit position.

    index reset is good for a small system (< 64). However, it will become very

    difficult to use if you have  > 100 reset. So we use register offset +
    bit position

    2. reset-lantiq.c does not support device restart which is part of the
    reset in

    old lantiq SoC. It moved this part into arch/mips/lantiq directory.

    3. reset-lantiqc reset callback doesn't implement what hardware implemented

    function. In old SoCs, some bits in the same register can be hardware
    reset clear.

    It just call assert + assert. For these SoCs, we should only call
    assert, hardware

    will auto deassert.

    4. Code not optimized and intel internal review not assessed.

    Based on the above findings, I would suggest reset-lantiq.c to move to
    reset-intel-syscon.c

    What is your opinion?


    Chuanhua

    >
    >
    > Martin
    >
    >
    > [0] https://wikidevi.com/wiki/Lantiq

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