Messages in this thread | | | Subject | Re: [PATCH v5 00/20] KVM RISC-V Support | From | Alexander Graf <> | Date | Fri, 23 Aug 2019 10:08:42 +0200 |
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On 22.08.19 10:42, Anup Patel wrote: > This series adds initial KVM RISC-V support. Currently, we are able to boot > RISC-V 64bit Linux Guests with multiple VCPUs. > > Few key aspects of KVM RISC-V added by this series are: > 1. Minimal possible KVM world-switch which touches only GPRs and few CSRs. > 2. Full Guest/VM switch is done via vcpu_get/vcpu_put infrastructure. > 3. KVM ONE_REG interface for VCPU register access from user-space. > 4. PLIC emulation is done in user-space. In-kernel PLIC emulation, will > be added in future. > 5. Timer and IPI emuation is done in-kernel. > 6. MMU notifiers supported. > 7. FP lazy save/restore supported. > 8. SBI v0.1 emulation for KVM Guest available. > > Here's a brief TODO list which we will work upon after this series: > 1. Handle trap from unpriv access in reading Guest instruction > 2. Handle trap from unpriv access in SBI v0.1 emulation > 3. Implement recursive stage2 page table programing > 4. SBI v0.2 emulation in-kernel > 5. SBI v0.2 hart hotplug emulation in-kernel > 6. In-kernel PLIC emulation > 7. ..... and more .....
Please consider patches I did not comment on as
Reviewed-by: Alexander Graf <graf@amazon.com>
Overall, I'm quite happy with the code. It's a very clean implementation of a KVM target.
The only major nit I have is the guest address space read: I don't think we should pull in code that we know allows user space to DOS the kernel. For that, we need to find an alternative. Either you implement a software page table walker and resolve VAs manually or you find a way to ensure that *any* exception taken during the read does not affect general code execution.
Thanks,
Alex
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