Messages in this thread Patch in this message | | | From | Sasha Levin <> | Subject | [PATCH 5.2 015/135] xtensa: add missing isync to the cpu_reset TLB code | Date | Thu, 22 Aug 2019 13:06:11 -0400 |
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From: Max Filippov <jcmvbkbc@gmail.com>
commit cd8869f4cb257f22b89495ca40f5281e58ba359c upstream.
ITLB entry modifications must be followed by the isync instruction before the new entries are possibly used. cpu_reset lacks one isync between ITLB way 6 initialization and jump to the identity mapping. Add missing isync to xtensa cpu_reset.
Cc: stable@vger.kernel.org Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> --- arch/xtensa/kernel/setup.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c index 176cb46bcf12c..0634bfb82a0bc 100644 --- a/arch/xtensa/kernel/setup.c +++ b/arch/xtensa/kernel/setup.c @@ -515,6 +515,7 @@ void cpu_reset(void) "add %2, %2, %7\n\t" "addi %0, %0, -1\n\t" "bnez %0, 1b\n\t" + "isync\n\t" /* Jump to identity mapping */ "jx %3\n" "2:\n\t" -- 2.20.1
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