Messages in this thread | | | From | Peng Fan <> | Subject | RE: [PATCH] clk: imx: pll14xx: avoid glitch when set rate | Date | Thu, 22 Aug 2019 09:18:10 +0000 |
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> Subject: Re: [PATCH] clk: imx: pll14xx: avoid glitch when set rate > > On 20.08.2019 05:17, Peng Fan wrote: > > According to PLL1443XA and PLL1416X spec, "When BYPASS is 0 and RESETB > > is changed from 0 to 1, FOUT starts to output unstable clock until > > lock time passes. PLL1416X/PLL1443XA may generate a glitch at FOUT." > > > > So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch. > > In the end of set rate, BYPASS will be cleared. > > > > @@ -191,6 +191,10 @@ static int clk_pll1416x_set_rate(struct clk_hw *hw, > unsigned long drate, > > tmp &= ~RST_MASK; > > writel_relaxed(tmp, pll->base); > > > > + /* Enable BYPASS */ > > + tmp |= BYPASS_MASK; > > + writel(tmp, pll->base); > > + > > Shouldn't BYPASS be set before reset?
No. the glitch happens when RESET changes from 0 to 1, not from 1 to 0.
> > Also, isn't a similar bypass/unbypass dance also needed in > clk_pll14xx_prepare? As far as I understand that could also output glitches > until the PLL is locked. It could be a separate patch.
Yes, that might also output glitch. Fix in v2.
> > It's strange that this BYPASS bit is also handled by muxes like > audio_pll1_bypass in clk-imx8mm.c but that's a separate issue not strictly > related to the glitches you're trying to fix here.
Yes, need use EXT_BYPASS for the mux usage.
Regards, Peng.
> > -- > Regards, > Leonard
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